Commit graph

14472 commits

Author SHA1 Message Date
Richard Henderson
3834cc6f8f target/sparc: Constify all Property and PropertyInfo
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:15 -06:00
Richard Henderson
a1eeba514f target/s390x: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:12 -06:00
Richard Henderson
f3ef448ac5 target/riscv: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:10 -06:00
Richard Henderson
b7ce9e19f4 target/mips: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:07 -06:00
Richard Henderson
f3d9225f6a target/microblaze: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:05 -06:00
Richard Henderson
032c2ec4ee target/i386: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:54:02 -06:00
Richard Henderson
ea1143358f target/hexagon: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:53:57 -06:00
Richard Henderson
1e2a0e1d9a target/avr: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:53:54 -06:00
Richard Henderson
eeed7aed06 target/arm: Constify all Property
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-15 12:53:43 -06:00
Stefan Hajnoczi
94b57605c1 target-arm queue:
* Finish conversion of A64 decoder to decodetree
  * Use float_round_to_odd in helper_fcvtx_f64_to_f32
  * Move TLBI insn emulation code out to its own source file
  * docs/system/arm: fix broken links, document undocumented properties
  * MAINTAINERS: correct an email address
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Merge tag 'pull-target-arm-20241213' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Finish conversion of A64 decoder to decodetree
 * Use float_round_to_odd in helper_fcvtx_f64_to_f32
 * Move TLBI insn emulation code out to its own source file
 * docs/system/arm: fix broken links, document undocumented properties
 * MAINTAINERS: correct an email address

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# gpg: Signature made Fri 13 Dec 2024 11:26:15 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20241213' of https://git.linaro.org/people/pmaydell/qemu-arm: (85 commits)
  target/arm: Simplify condition for tlbi_el2_cp_reginfo[]
  target/arm: Move RME TLB insns to tlb-insns.c
  target/arm: Move small helper functions to tlb-insns.c
  target/arm: Move the TLBI OS insns to tlb-insns.c.
  target/arm: Move TLBI range insns
  target/arm: Move AArch64 EL3 TLBI insns
  target/arm: Move the AArch64 EL2 TLBI insns
  target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[]
  target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c
  target/arm: Move some TLBI insns to their own source file
  MAINTAINERS: correct my email address
  docs/system/arm/virt: document missing properties
  docs/system/arm/xlnx-versal-virt: document ospi-flash property
  docs/system/arm/fby35: document execute-in-place property
  docs/system/arm/orangepi: update links
  target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32
  target/arm: Convert FCVTL to decodetree
  target/arm: Convert URECPE and URSQRTE to decodetree
  target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte
  target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-14 08:42:15 -05:00
Stefan Hajnoczi
7fa7aa8114 Remove HEX_DEBUG, EXCP/CAUSE fixes
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Merge tag 'pull-hex-20241212' of https://github.com/quic/qemu into staging

Remove HEX_DEBUG, EXCP/CAUSE fixes

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# gpg: Signature made Thu 12 Dec 2024 23:17:50 EST
# gpg:                using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg:                 aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg:                 aka "bcain" [unknown]
# gpg:                 aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20241212' of https://github.com/quic/qemu:
  target/hexagon: Make HVX vector args. restrict *
  target/hexagon: Use argparse in all python scripts
  target/hexagon: add enums for event, cause
  target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*
  Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-14 08:36:05 -05:00
Peter Maydell
48e652c4bd target/arm: Simplify condition for tlbi_el2_cp_reginfo[]
We currently register the tlbi_el2_cp_reginfo[] TLBI insns if EL2 is
implemented, or if EL3 and v8 is implemented.  This is a copy of the
logic used for el2_cp_reginfo[], but for the specific case of the
TLBI insns we can simplify it.  This is because we do not need the
"if EL2 does not exist but EL3 does then EL2 registers should exist
and be RAZ/WI" handling here: all our cpregs are for instructions,
which UNDEF when EL3 exists and EL2 does not.

Simplify the condition down to just "if EL2 exists".
This is not a behaviour change because:
 * for AArch64 insns we marked them with ARM_CP_EL3_NO_EL2_UNDEF,
   which meant that define_arm_cp_regs() would ignore them if
   EL2 wasn't present
 * for AArch32 insns, the .access = PL2_W meant that if EL2
   was not present the only way to get at them was from AArch32
   EL3; but we have no CPUs which have ARM_FEATURE_V8 but
   start in AArch32

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-11-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
0b7aefb9eb target/arm: Move RME TLB insns to tlb-insns.c
Move the FEAT_RME specific TLB insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-10-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
27fb860fd4 target/arm: Move small helper functions to tlb-insns.c
The remaining functions that we temporarily made global are now
used only from callsits in tlb-insns.c; move them across and
make them file-local again.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-9-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
b0f7cd3572 target/arm: Move the TLBI OS insns to tlb-insns.c.
Move the TLBI OS insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-8-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
6559379957 target/arm: Move TLBI range insns
Move the TLBI invalidate-range insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-7-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
5991e5abe3 target/arm: Move AArch64 EL3 TLBI insns
Move the AArch64 EL3 TLBI insns from el3_cp_reginfo[] across
to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-6-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
7cadf1139d target/arm: Move the AArch64 EL2 TLBI insns
Move the AArch64 EL2 TLBI insn definitions that were
in el2_cp_reginfo[] across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-5-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
abbb82646a target/arm: Move AArch64 TLBI insns from v8_cp_reginfo[]
Move the AArch64 TLBI insns that are declared in v8_cp_reginfo[]
into tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-4-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
d6b6da1fc8 target/arm: Move TLBI insns for AArch32 EL2 to tlbi_insn_helper.c
Move the AArch32 TLBI insns for AArch32 EL2 to tlbi_insn_helper.c.
To keep this as an obviously pure code-movement, we retain the
same condition for registering tlbi_el2_cp_reginfo that we use for
el2_cp_reginfo. We'll be able to simplify this condition later,
since the need to define the reginfo for EL3-without-EL2 doesn't
apply for the TLBI ops specifically.

This move brings all the uses of tlbimva_hyp_write() and
tlbimva_hyp_is_write() back into a single file, so we can move those
also, and make them file-local again.

The helper alle1_tlbmask() is an exception to the pattern that we
only need to make these functions global temporarily, because once
this refactoring is complete it will be called by both code in
helper.c (vttbr_write()) and by code in tlb-insns.c.  We therefore
put its prototype in a permanent home in internals.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-3-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Peter Maydell
1e32ee23cd target/arm: Move some TLBI insns to their own source file
target/arm/helper.c is very large and unwieldy.  One subset of code
that we can pull out into its own file is the cpreg arrays and
corresponding functions for the TLBI instructions.

Because these are instructions they are only relevant for TCG and we
can make the new file only be built for CONFIG_TCG.

In this commit we move the AArch32 instructions from:
 not_v7_cp_reginfo[]
 v7_cp_reginfo[]
 v7mp_cp_reginfo[]
 v8_cp_reginfo[]
into a new file target/arm/tcg/tlb-insns.c.

A few small functions are used both by functions we haven't yet moved
across and by functions we have already moved.  We temporarily make
these global with a prototype in cpregs.h; when the move of all TLBI
insns is complete these will return to being file-local.

For CONFIG_TCG, this is just moving code around.  For a KVM only
build, these cpregs will no longer be added to the cpregs hashtable
for the CPU.  However this should not be a behaviour change, because:
 * we never try to migration sync or otherwise include
   ARM_CP_NO_RAW cpregs
 * for migration we treat the kernel's list of system registers
   as the authoritative one, so these TLBI insns were never
   in it anyway
The no-tcg stub of define_tlb_insn_regs() therefore does nothing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-2-peter.maydell@linaro.org
2024-12-13 15:41:09 +00:00
Richard Henderson
c66be53ce7 target/arm: Use float_round_to_odd in helper_fcvtx_f64_to_f32
Softfloat has native support for round-to-odd.  Use it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241206031428.78634-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 15:32:55 +00:00
Richard Henderson
53ac794af6 target/arm: Convert FCVTL to decodetree
Remove lookup_disas_fn, handle_2misc_widening,
disas_simd_two_reg_misc, disas_data_proc_simd,
disas_data_proc_simd_fp, disas_a64_legacy, as
this is the final insn to be converted.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-70-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
4280c9b5af target/arm: Convert URECPE and URSQRTE to decodetree
Remove handle_2misc_reciprocal as these were the last
insns decoded by that function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-69-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
8710a43de1 target/arm: Introduce gen_gvec_urecpe, gen_gvec_ursqrte
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-68-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
31e65acf7b target/arm: Convert FRECPE, FRECPX, FRSQRTE to decodetree
Remove disas_simd_scalar_two_reg_misc and
disas_simd_two_reg_misc_fp16 as these were the
last insns decoded by those functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-67-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
df112a2578 target/arm: Convert handle_2misc_fcmp_zero to decodetree
This includes FCMEQ, FCMGT, FCMGE, FCMLT, FCMLE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-66-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
475dbea47d target/arm: Convert FCVT* (vector, integer) to decodetree
Remove handle_2misc_64 as these were the last insns decoded
by that function.  Remove helper_advsimd_f16to[su]inth as unused;
we now always go through helper_vfp_to[su]hh or a specialized
vector function instead.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-65-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
9a93223c86 target/arm: Convert FCVTZ[SU] (vector, fixed-point) to decodetree
Remove handle_simd_shift_fpint_conv and disas_simd_shift_imm
as these were the last insns decoded by those functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-64-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
53b9486be7 target/arm: Convert [US]CVTF (vector) to decodetree
Remove handle_simd_intfp_conv and handle_simd_shift_intfp_conv
as these were the last insns decoded by those functions.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-63-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
c2e1338816 target/arm: Rename helper_gvec_vcvt_[hf][su] with _rz
Emphasize that these functions use round-to-zero mode.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-62-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
69d5391a66 target/arm: Convert [US]CVTF (vector, fixed-point) scalar to decodetree
Remove disas_simd_scalar_shift_imm as these were the
last insns decoded by that function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-61-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
f469ca170d target/arm: Convert [US]CVTF (vector, integer) scalar to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-60-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:24 +00:00
Richard Henderson
6697b35e98 target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-59-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
fe78ebaae9 target/arm: Convert FCVT* (vector, integer) scalar to decodetree
Arm silliness with naming, the scalar insns described
as part of the vector instructions, as separate from
the "regular" scalar insns which output to general registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-58-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
09facda342 target/arm: Convert FRINT* (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-57-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
73a6f0c245 target/arm: Convert FSQRT (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
ea30b3522a target/arm: Convert FABS, FNEG (vector) to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-55-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
f0632d48a7 target/arm: Implement gen_gvec_fabs, gen_gvec_fneg
Move the current implementation out of translate-neon.c,
and extend to handle all element sizes.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-54-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
a05c56178a target/arm: Convert SHLL to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
1fd9aa0b89 target/arm: Convert FCVTXN to decodetree
Remove handle_2misc_narrow as this was the last insn decoded
by that function.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-52-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
febacdb237 target/arm: Convert FCVTN, BFCVTN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-51-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
fbbc0b2c8a target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
ace363a1e9 target/arm: Introduce clear_vec
In a couple of places, clearing the entire vector before storing one
element is the easiest solution.  Wrap that into a helper function.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-49-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
07e0d7a0c7 target/arm: Remove helper_neon_{add,sub}l_u{16,32}
These have generic equivalents: tcg_gen_vec_{add,sub}{16,32}_i64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-48-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
09e7f80e58 target/arm: Convert handle_2misc_pairwise to decodetree
This includes SADDLP, UADDLP, SADALP, UADALP.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-47-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
c14bde6998 target/arm: Introduce gen_gvec_{s,u}{add,ada}lp
Pairwise addition with and without accumulation.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
e90cf92209 target/arm: Move helper_neon_addlp_{s8, s16} to neon_helper.c
Move from helper-a64.c to neon_helper.c so that these
functions are available for arm32 code as well.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
7c6bdcdaed target/arm: Convert handle_rev to decodetree
This includes REV16, REV32, REV64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00
Richard Henderson
38f9950c8e target/arm: Introduce gen_gvec_rev{16,32,64}
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13 13:39:23 +00:00