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target/arm: Convert FCVT* (vector, fixed-point) scalar to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-59-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:25 -06:00 • committed by Peter Maydell
parent fe78ebaae9
commit 6697b35e98
2 changed files with 20 additions and 3 deletions
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19
target/arm/tcg/a64.decode
View file

@ -1682,6 +1682,25 @@ FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h
FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
%fcvt_f_sh_h 16:4 !function=rsub_16
%fcvt_f_sh_s 16:5 !function=rsub_32
%fcvt_f_sh_d 16:6 !function=rsub_64
@fcvt_fixed_h .... .... . 001 .... ...... rn:5 rd:5 \
&fcvt sf=0 esz=1 shift=%fcvt_f_sh_h
@fcvt_fixed_s .... .... . 01 ..... ...... rn:5 rd:5 \
&fcvt sf=0 esz=2 shift=%fcvt_f_sh_s
@fcvt_fixed_d .... .... . 1 ...... ...... rn:5 rd:5 \
&fcvt sf=0 esz=3 shift=%fcvt_f_sh_d
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
FCVTZS_f 0101 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_h
FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_s
FCVTZU_f 0111 1111 0 ....... 111111 ..... ..... @fcvt_fixed_d
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e

4
target/arm/tcg/translate-a64.c
View file

@ -9535,9 +9535,6 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
opcode, rn, rd);
break;
case 0x1f: /* FCVTZS, FCVTZU */
handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
break;
default:
case 0x00: /* SSHR / USHR */
case 0x02: /* SSRA / USRA */
@ -9551,6 +9548,7 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
case 0x11: /* SQRSHRUN */
case 0x12: /* SQSHRN, UQSHRN */
case 0x13: /* SQRSHRN, UQRSHRN */
case 0x1f: /* FCVTZS, FCVTZU */
unallocated_encoding(s);
break;
}