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target/arm: Convert FCVT* (vector, integer) scalar to decodetree
Arm silliness with naming, the scalar insns described as part of the vector instructions, as separate from the "regular" scalar insns which output to general registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-58-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
09facda342
commit
fe78ebaae9
2 changed files with 86 additions and 77 deletions
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@ -1652,6 +1652,36 @@ UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
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FCVTXN_s 0111 1110 011 00001 01101 0 ..... ..... @rr_s
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@icvt_h . ....... .. ...... ...... rn:5 rd:5 \
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&fcvt sf=0 esz=1 shift=0
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@icvt_sd . ....... .. ...... ...... rn:5 rd:5 \
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&fcvt sf=0 esz=%esz_sd shift=0
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FCVTNS_f 0101 1110 011 11001 10101 0 ..... ..... @icvt_h
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FCVTNS_f 0101 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
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FCVTNU_f 0111 1110 011 11001 10101 0 ..... ..... @icvt_h
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FCVTNU_f 0111 1110 0.1 00001 10101 0 ..... ..... @icvt_sd
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FCVTPS_f 0101 1110 111 11001 10101 0 ..... ..... @icvt_h
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FCVTPS_f 0101 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
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FCVTPU_f 0111 1110 111 11001 10101 0 ..... ..... @icvt_h
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FCVTPU_f 0111 1110 1.1 00001 10101 0 ..... ..... @icvt_sd
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FCVTMS_f 0101 1110 011 11001 10111 0 ..... ..... @icvt_h
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FCVTMS_f 0101 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
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FCVTMU_f 0111 1110 011 11001 10111 0 ..... ..... @icvt_h
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FCVTMU_f 0111 1110 0.1 00001 10111 0 ..... ..... @icvt_sd
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FCVTZS_f 0101 1110 111 11001 10111 0 ..... ..... @icvt_h
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FCVTZS_f 0101 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
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FCVTZU_f 0111 1110 111 11001 10111 0 ..... ..... @icvt_h
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FCVTZU_f 0111 1110 1.1 00001 10111 0 ..... ..... @icvt_sd
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FCVTAS_f 0101 1110 011 11001 11001 0 ..... ..... @icvt_h
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FCVTAS_f 0101 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
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FCVTAU_f 0111 1110 011 11001 11001 0 ..... ..... @icvt_h
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FCVTAU_f 0111 1110 0.1 00001 11001 0 ..... ..... @icvt_sd
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# Advanced SIMD two-register miscellaneous
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SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
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@ -8674,6 +8674,16 @@ static void do_fcvt_scalar(DisasContext *s, MemOp out, MemOp esz,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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case MO_16 | MO_SIGN:
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gen_helper_vfp_toshh(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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case MO_16:
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gen_helper_vfp_touhh(tcg_single, tcg_single,
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tcg_shift, tcg_fpstatus);
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tcg_gen_extu_i32_i64(tcg_out, tcg_single);
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break;
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default:
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g_assert_not_reached();
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}
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@ -8717,6 +8727,42 @@ TRANS(FCVTZU_g, do_fcvt_g, a, FPROUNDING_ZERO, false)
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TRANS(FCVTAS_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, true)
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TRANS(FCVTAU_g, do_fcvt_g, a, FPROUNDING_TIEAWAY, false)
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/*
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* FCVT* (vector), scalar version.
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* Which sounds weird, but really just means output to fp register
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* instead of output to general register. Input and output element
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* size are always equal.
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*/
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static bool do_fcvt_f(DisasContext *s, arg_fcvt *a,
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ARMFPRounding rmode, bool is_signed)
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{
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TCGv_i64 tcg_int;
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int check = fp_access_check_scalar_hsd(s, a->esz);
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if (check <= 0) {
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return check == 0;
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}
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tcg_int = tcg_temp_new_i64();
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do_fcvt_scalar(s, a->esz | (is_signed ? MO_SIGN : 0),
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a->esz, tcg_int, a->shift, a->rn, rmode);
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clear_vec(s, a->rd);
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write_vec_element(s, tcg_int, a->rd, 0, a->esz);
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return true;
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}
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TRANS(FCVTNS_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, true)
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TRANS(FCVTNU_f, do_fcvt_f, a, FPROUNDING_TIEEVEN, false)
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TRANS(FCVTPS_f, do_fcvt_f, a, FPROUNDING_POSINF, true)
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TRANS(FCVTPU_f, do_fcvt_f, a, FPROUNDING_POSINF, false)
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TRANS(FCVTMS_f, do_fcvt_f, a, FPROUNDING_NEGINF, true)
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TRANS(FCVTMU_f, do_fcvt_f, a, FPROUNDING_NEGINF, false)
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TRANS(FCVTZS_f, do_fcvt_f, a, FPROUNDING_ZERO, true)
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TRANS(FCVTZU_f, do_fcvt_f, a, FPROUNDING_ZERO, false)
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TRANS(FCVTAS_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, true)
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TRANS(FCVTAU_f, do_fcvt_f, a, FPROUNDING_TIEAWAY, false)
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static bool trans_FJCVTZS(DisasContext *s, arg_FJCVTZS *a)
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{
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if (!dc_isar_feature(aa64_jscvt, s)) {
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@ -9776,10 +9822,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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int opcode = extract32(insn, 12, 5);
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int size = extract32(insn, 22, 2);
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bool u = extract32(insn, 29, 1);
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bool is_fcvt = false;
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int rmode;
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TCGv_i32 tcg_rmode;
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TCGv_ptr tcg_fpstatus;
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switch (opcode) {
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case 0xc ... 0xf:
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@ -9824,15 +9866,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x5b: /* FCVTMU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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is_fcvt = true;
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rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
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break;
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case 0x1c: /* FCVTAS */
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case 0x5c: /* FCVTAU */
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/* TIEAWAY doesn't fit in the usual rounding mode encoding */
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is_fcvt = true;
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rmode = FPROUNDING_TIEAWAY;
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break;
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case 0x56: /* FCVTXN, FCVTXN2 */
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default:
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unallocated_encoding(s);
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@ -9851,59 +9886,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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if (is_fcvt) {
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tcg_fpstatus = fpstatus_ptr(FPST_FPCR);
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tcg_rmode = gen_set_rmode(rmode, tcg_fpstatus);
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} else {
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tcg_fpstatus = NULL;
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tcg_rmode = NULL;
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}
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if (size == 3) {
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TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
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write_fp_dreg(s, rd, tcg_rd);
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} else {
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TCGv_i32 tcg_rn = tcg_temp_new_i32();
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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read_vec_element_i32(s, tcg_rn, rn, 0, size);
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switch (opcode) {
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0),
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tcg_fpstatus);
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break;
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0),
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tcg_fpstatus);
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break;
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default:
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case 0x7: /* SQABS, SQNEG */
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g_assert_not_reached();
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}
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write_fp_sreg(s, rd, tcg_rd);
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}
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if (is_fcvt) {
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gen_restore_rmode(tcg_rmode, tcg_fpstatus);
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}
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g_assert_not_reached();
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}
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/* AdvSIMD shift by immediate
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@ -10391,30 +10374,26 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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switch (fpop) {
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x3d: /* FRECPE */
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gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x3f: /* FRECPX */
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gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x7d: /* FRSQRTE */
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gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
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break;
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default:
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
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break;
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case 0x7d: /* FRSQRTE */
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gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
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break;
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default:
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g_assert_not_reached();
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}
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