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target/arm: Move small helper functions to tlb-insns.c
The remaining functions that we temporarily made global are now used only from callsits in tlb-insns.c; move them across and make them file-local again. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241210160452.2427965-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
b0f7cd3572
commit
27fb860fd4
3 changed files with 220 additions and 254 deletions
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@ -1134,38 +1134,4 @@ static inline bool arm_cpreg_traps_in_nv(const ARMCPRegInfo *ri)
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return ri->opc1 == 4 || ri->opc1 == 5;
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}
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/*
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* Temporary declarations of functions until the move to tlb_insn_helper.c
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* is complete and we can make the functions static again
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*/
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CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread);
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CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread);
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CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread);
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bool tlb_force_broadcast(CPUARMState *env);
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int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint64_t addr);
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int vae1_tlbbits(CPUARMState *env, uint64_t addr);
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int vae2_tlbbits(CPUARMState *env, uint64_t addr);
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int vae1_tlbmask(CPUARMState *env);
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int vae2_tlbmask(CPUARMState *env);
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int ipas2e1_tlbmask(CPUARMState *env, int64_t value);
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int e2_tlbmask(CPUARMState *env);
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void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value);
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#endif /* TARGET_ARM_CPREGS_H */
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@ -365,40 +365,6 @@ static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri,
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TTLB. */
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CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
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CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 &&
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(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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#ifdef TARGET_AARCH64
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/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
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CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 &&
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(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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#endif
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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ARMCPU *cpu = env_archcpu(env);
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@ -455,16 +421,6 @@ int alle1_tlbmask(CPUARMState *env)
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ARMMMUIdxBit_Stage2_S);
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}
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/*
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* Non-IS variants of TLB operations are upgraded to
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* IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
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* force broadcast of these operations.
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*/
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bool tlb_force_broadcast(CPUARMState *env)
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{
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return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
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}
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static const ARMCPRegInfo cp_reginfo[] = {
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/*
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* Define the secure and non-secure FCSE identifier CP registers
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@ -4680,182 +4636,6 @@ static CPAccessResult access_tocu(CPUARMState *env, const ARMCPRegInfo *ri,
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return do_cacheop_pou_access(env, HCR_TOCU | HCR_TPU);
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}
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/*
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* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
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* Page D4-1736 (DDI0487A.b)
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*/
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int vae1_tlbmask(CPUARMState *env)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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uint16_t mask;
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assert(arm_feature(env, ARM_FEATURE_AARCH64));
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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/* This is AArch64 only, so we don't need to touch the EL30_x TLBs */
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mask = ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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}
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return mask;
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}
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int vae2_tlbmask(CPUARMState *env)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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uint16_t mask;
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if (hcr & HCR_E2H) {
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mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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mask = ARMMMUIdxBit_E2;
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}
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return mask;
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}
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/* Return 56 if TBI is enabled, 64 otherwise. */
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int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint64_t addr)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx);
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int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
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int select = extract64(addr, 55, 1);
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return (tbi >> select) & 1 ? 56 : 64;
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}
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int vae1_tlbbits(CPUARMState *env, uint64_t addr)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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ARMMMUIdx mmu_idx;
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assert(arm_feature(env, ARM_FEATURE_AARCH64));
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/* Only the regime of the mmu_idx below is significant. */
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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mmu_idx = ARMMMUIdx_E20_0;
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} else {
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mmu_idx = ARMMMUIdx_E10_0;
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}
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return tlbbits_for_regime(env, mmu_idx, addr);
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}
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int vae2_tlbbits(CPUARMState *env, uint64_t addr)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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ARMMMUIdx mmu_idx;
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/*
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* Only the regime of the mmu_idx below is significant.
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* Regime EL2&0 has two ranges with separate TBI configuration, while EL2
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* only has one.
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*/
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if (hcr & HCR_E2H) {
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mmu_idx = ARMMMUIdx_E20_2;
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} else {
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mmu_idx = ARMMMUIdx_E2;
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}
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return tlbbits_for_regime(env, mmu_idx, addr);
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}
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void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = vae1_tlbmask(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
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}
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int e2_tlbmask(CPUARMState *env)
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{
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return (ARMMMUIdxBit_E20_0 |
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ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E2);
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}
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void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = alle1_tlbmask(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
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}
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void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = e2_tlbmask(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
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}
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void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
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}
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void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = vae1_tlbmask(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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int bits = vae1_tlbbits(env, pageaddr);
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tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
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}
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void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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int mask = vae2_tlbmask(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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int bits = vae2_tlbbits(env, pageaddr);
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tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
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}
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void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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CPUState *cs = env_cpu(env);
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uint64_t pageaddr = sextract64(value << 12, 0, 56);
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int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
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tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
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ARMMMUIdxBit_E3, bits);
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}
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int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
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{
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/*
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* The MSB of value is the NS field, which only applies if SEL2
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* is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
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*/
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return (value >= 0
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&& cpu_isar_feature(aa64_sel2, env_archcpu(env))
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&& arm_is_secure_below_el3(env)
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? ARMMMUIdxBit_Stage2_S
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: ARMMMUIdxBit_Stage2);
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}
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static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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@ -13,6 +13,40 @@
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#include "cpu-features.h"
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#include "cpregs.h"
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/* Check for traps from EL1 due to HCR_EL2.TTLB. */
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static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_TTLB)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBIS. */
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static CPAccessResult access_ttlbis(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 &&
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(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBIS))) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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#ifdef TARGET_AARCH64
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/* Check for traps from EL1 due to HCR_EL2.TTLB or TTLBOS. */
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static CPAccessResult access_ttlbos(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 1 &&
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(arm_hcr_el2_eff(env) & (HCR_TTLB | HCR_TTLBOS))) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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#endif
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/* IS variants of TLB operations must affect all cores */
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static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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@ -46,6 +80,16 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK);
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}
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/*
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* Non-IS variants of TLB operations are upgraded to
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* IS versions if we are at EL1 and HCR_EL2.FB is effectively set to
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* force broadcast of these operations.
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*/
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static bool tlb_force_broadcast(CPUARMState *env)
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{
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return arm_current_el(env) == 1 && (arm_hcr_el2_eff(env) & HCR_FB);
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}
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static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -170,6 +214,102 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
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tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
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}
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/*
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* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
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* Page D4-1736 (DDI0487A.b)
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*/
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static int vae1_tlbmask(CPUARMState *env)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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uint16_t mask;
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assert(arm_feature(env, ARM_FEATURE_AARCH64));
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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/* This is AArch64 only, so we don't need to touch the EL30_x TLBs */
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mask = ARMMMUIdxBit_E10_1 |
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ARMMMUIdxBit_E10_1_PAN |
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ARMMMUIdxBit_E10_0;
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}
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return mask;
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}
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static int vae2_tlbmask(CPUARMState *env)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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uint16_t mask;
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if (hcr & HCR_E2H) {
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mask = ARMMMUIdxBit_E20_2 |
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ARMMMUIdxBit_E20_2_PAN |
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ARMMMUIdxBit_E20_0;
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} else {
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mask = ARMMMUIdxBit_E2;
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}
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return mask;
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}
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/* Return 56 if TBI is enabled, 64 otherwise. */
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static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx,
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uint64_t addr)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx);
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int tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
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int select = extract64(addr, 55, 1);
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return (tbi >> select) & 1 ? 56 : 64;
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}
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static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
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ARMMMUIdx mmu_idx;
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assert(arm_feature(env, ARM_FEATURE_AARCH64));
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/* Only the regime of the mmu_idx below is significant. */
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if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
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mmu_idx = ARMMMUIdx_E20_0;
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} else {
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mmu_idx = ARMMMUIdx_E10_0;
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}
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return tlbbits_for_regime(env, mmu_idx, addr);
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}
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static int vae2_tlbbits(CPUARMState *env, uint64_t addr)
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{
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uint64_t hcr = arm_hcr_el2_eff(env);
|
||||
ARMMMUIdx mmu_idx;
|
||||
|
||||
/*
|
||||
* Only the regime of the mmu_idx below is significant.
|
||||
* Regime EL2&0 has two ranges with separate TBI configuration, while EL2
|
||||
* only has one.
|
||||
*/
|
||||
if (hcr & HCR_E2H) {
|
||||
mmu_idx = ARMMMUIdx_E20_2;
|
||||
} else {
|
||||
mmu_idx = ARMMMUIdx_E2;
|
||||
}
|
||||
|
||||
return tlbbits_for_regime(env, mmu_idx, addr);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = vae1_tlbmask(env);
|
||||
|
||||
tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
|
|
@ -183,6 +323,14 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
}
|
||||
}
|
||||
|
||||
static int e2_tlbmask(CPUARMState *env)
|
||||
{
|
||||
return (ARMMMUIdxBit_E20_0 |
|
||||
ARMMMUIdxBit_E20_2 |
|
||||
ARMMMUIdxBit_E20_2_PAN |
|
||||
ARMMMUIdxBit_E2);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
|
|
@ -210,6 +358,32 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = alle1_tlbmask(env);
|
||||
|
||||
tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = e2_tlbmask(env);
|
||||
|
||||
tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
|
||||
tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
|
|
@ -241,6 +415,17 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = vae1_tlbmask(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = vae1_tlbbits(env, pageaddr);
|
||||
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
|
|
@ -262,6 +447,41 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
|||
}
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
int mask = vae2_tlbmask(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = vae2_tlbbits(env, pageaddr);
|
||||
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
CPUState *cs = env_cpu(env);
|
||||
uint64_t pageaddr = sextract64(value << 12, 0, 56);
|
||||
int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
|
||||
|
||||
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
|
||||
ARMMMUIdxBit_E3, bits);
|
||||
}
|
||||
|
||||
static int ipas2e1_tlbmask(CPUARMState *env, int64_t value)
|
||||
{
|
||||
/*
|
||||
* The MSB of value is the NS field, which only applies if SEL2
|
||||
* is implemented and SCR_EL3.NS is not set (i.e. in secure mode).
|
||||
*/
|
||||
return (value >= 0
|
||||
&& cpu_isar_feature(aa64_sel2, env_archcpu(env))
|
||||
&& arm_is_secure_below_el3(env)
|
||||
? ARMMMUIdxBit_Stage2_S
|
||||
: ARMMMUIdxBit_Stage2);
|
||||
}
|
||||
|
||||
static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
|
||||
uint64_t value)
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue