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target/arm: Convert FCVT* (vector, integer) to decodetree
Remove handle_2misc_64 as these were the last insns decoded by that function. Remove helper_advsimd_f16to[su]inth as unused; we now always go through helper_vfp_to[su]hh or a specialized vector function instead. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211163036.2297116-65-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
9a93223c86
commit
475dbea47d
6 changed files with 102 additions and 188 deletions
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@ -665,6 +665,8 @@ DEF_HELPER_FLAGS_4(gvec_vcvt_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rz_ds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rz_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sd, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ud, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rm_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rm_us, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(gvec_vcvt_rm_sh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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@ -1793,6 +1793,31 @@ SCVTF_vi 0.00 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
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UCVTF_vi 0.10 1110 011 11001 11011 0 ..... ..... @qrr_h
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UCVTF_vi 0.10 1110 0.1 00001 11011 0 ..... ..... @qrr_sd
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FCVTNS_vi 0.00 1110 011 11001 10101 0 ..... ..... @qrr_h
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FCVTNS_vi 0.00 1110 0.1 00001 10101 0 ..... ..... @qrr_sd
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FCVTNU_vi 0.10 1110 011 11001 10101 0 ..... ..... @qrr_h
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FCVTNU_vi 0.10 1110 0.1 00001 10101 0 ..... ..... @qrr_sd
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FCVTPS_vi 0.00 1110 111 11001 10101 0 ..... ..... @qrr_h
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FCVTPS_vi 0.00 1110 1.1 00001 10101 0 ..... ..... @qrr_sd
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FCVTPU_vi 0.10 1110 111 11001 10101 0 ..... ..... @qrr_h
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FCVTPU_vi 0.10 1110 1.1 00001 10101 0 ..... ..... @qrr_sd
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FCVTMS_vi 0.00 1110 011 11001 10111 0 ..... ..... @qrr_h
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FCVTMS_vi 0.00 1110 0.1 00001 10111 0 ..... ..... @qrr_sd
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FCVTMU_vi 0.10 1110 011 11001 10111 0 ..... ..... @qrr_h
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FCVTMU_vi 0.10 1110 0.1 00001 10111 0 ..... ..... @qrr_sd
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FCVTZS_vi 0.00 1110 111 11001 10111 0 ..... ..... @qrr_h
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FCVTZS_vi 0.00 1110 1.1 00001 10111 0 ..... ..... @qrr_sd
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FCVTZU_vi 0.10 1110 111 11001 10111 0 ..... ..... @qrr_h
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FCVTZU_vi 0.10 1110 1.1 00001 10111 0 ..... ..... @qrr_sd
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FCVTAS_vi 0.00 1110 011 11001 11001 0 ..... ..... @qrr_h
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FCVTAS_vi 0.00 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
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FCVTAU_vi 0.10 1110 011 11001 11001 0 ..... ..... @qrr_h
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FCVTAU_vi 0.10 1110 0.1 00001 11001 0 ..... ..... @qrr_sd
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&fcvt_q rd rn esz q shift
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@fcvtq_h . q:1 . ...... 001 .... ...... rn:5 rd:5 \
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&fcvt_q esz=1 shift=%fcvt_f_sh_h
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@ -618,38 +618,6 @@ uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
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return ret;
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}
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/*
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* Half-precision floating point conversion functions
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*
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* There are a multitude of conversion functions with various
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* different rounding modes. This is dealt with by the calling code
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* setting the mode appropriately before calling the helper.
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*/
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uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
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{
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float_status *fpst = fpstp;
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/* Invalid if we are passed a NaN */
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if (float16_is_any_nan(a)) {
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float_raise(float_flag_invalid, fpst);
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return 0;
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}
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return float16_to_int16(a, fpst);
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}
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uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
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{
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float_status *fpst = fpstp;
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/* Invalid if we are passed a NaN */
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if (float16_is_any_nan(a)) {
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float_raise(float_flag_invalid, fpst);
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return 0;
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}
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return float16_to_uint16(a, fpst);
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}
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static int el_from_spsr(uint32_t spsr)
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{
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/* Return the exception level that this SPSR is requesting a return to,
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@ -74,8 +74,6 @@ DEF_HELPER_3(advsimd_mulx2h, i32, i32, i32, ptr)
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DEF_HELPER_4(advsimd_muladd2h, i32, i32, i32, i32, ptr)
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DEF_HELPER_2(advsimd_rinth_exact, f16, f16, ptr)
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DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
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DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
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DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
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DEF_HELPER_2(exception_return, void, env, i64)
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DEF_HELPER_FLAGS_2(dc_zva, TCG_CALL_NO_WG, void, env, i64)
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@ -9348,56 +9348,38 @@ static gen_helper_gvec_2_ptr * const f_fcvtzu_vf[] = {
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TRANS(FCVTZU_vf, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, a->shift, f_fcvtzu_vf)
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static void handle_2misc_64(DisasContext *s, int opcode, bool u,
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TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
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TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
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{
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/* Handle 64->64 opcodes which are shared between the scalar and
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* vector 2-reg-misc groups. We cover every integer opcode where size == 3
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* is valid in either group and also the double-precision fp ops.
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* The caller only need provide tcg_rmode and tcg_fpstatus if the op
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* requires them.
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*/
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switch (opcode) {
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
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break;
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpstatus);
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break;
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default:
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case 0x4: /* CLS, CLZ */
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case 0x5: /* NOT */
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case 0x7: /* SQABS, SQNEG */
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case 0x8: /* CMGT, CMGE */
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case 0x9: /* CMEQ, CMLE */
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case 0xa: /* CMLT */
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case 0xb: /* ABS, NEG */
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case 0x2f: /* FABS */
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case 0x6f: /* FNEG */
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case 0x7f: /* FSQRT */
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case 0x18: /* FRINTN */
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case 0x19: /* FRINTM */
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case 0x38: /* FRINTP */
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case 0x39: /* FRINTZ */
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case 0x58: /* FRINTA */
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case 0x79: /* FRINTI */
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case 0x59: /* FRINTX */
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case 0x1e: /* FRINT32Z */
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case 0x5e: /* FRINT32X */
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case 0x1f: /* FRINT64Z */
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case 0x5f: /* FRINT64X */
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g_assert_not_reached();
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}
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}
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static gen_helper_gvec_2_ptr * const f_fcvt_s_vi[] = {
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gen_helper_gvec_vcvt_rm_sh,
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gen_helper_gvec_vcvt_rm_ss,
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gen_helper_gvec_vcvt_rm_sd,
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};
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static gen_helper_gvec_2_ptr * const f_fcvt_u_vi[] = {
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gen_helper_gvec_vcvt_rm_uh,
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gen_helper_gvec_vcvt_rm_us,
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gen_helper_gvec_vcvt_rm_ud,
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};
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TRANS(FCVTNS_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_nearest_even, f_fcvt_s_vi)
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TRANS(FCVTNU_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_nearest_even, f_fcvt_u_vi)
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TRANS(FCVTPS_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_up, f_fcvt_s_vi)
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TRANS(FCVTPU_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_up, f_fcvt_u_vi)
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TRANS(FCVTMS_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_down, f_fcvt_s_vi)
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TRANS(FCVTMU_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_down, f_fcvt_u_vi)
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TRANS(FCVTZS_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_to_zero, f_fcvt_s_vi)
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TRANS(FCVTZU_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_to_zero, f_fcvt_u_vi)
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TRANS(FCVTAS_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_ties_away, f_fcvt_s_vi)
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TRANS(FCVTAU_vi, do_gvec_op2_fpst,
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a->esz, a->q, a->rd, a->rn, float_round_ties_away, f_fcvt_u_vi)
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static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
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bool is_scalar, bool is_u, bool is_q,
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@ -9758,30 +9740,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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}
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handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
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return;
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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need_fpstatus = true;
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rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x5c: /* FCVTAU */
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case 0x1c: /* FCVTAS */
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need_fpstatus = true;
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rmode = FPROUNDING_TIEAWAY;
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if (size == 3 && !is_q) {
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unallocated_encoding(s);
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return;
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}
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break;
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case 0x3c: /* URECPE */
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if (size == 3) {
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unallocated_encoding(s);
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@ -9831,6 +9789,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x5f: /* FRINT64X */
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case 0x1d: /* SCVTF */
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case 0x5d: /* UCVTF */
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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case 0x5c: /* FCVTAU */
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case 0x1c: /* FCVTAS */
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unallocated_encoding(s);
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return;
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}
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@ -9871,26 +9839,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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tcg_rmode = NULL;
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}
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if (size == 3) {
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/* All 64-bit element operations can be shared with scalar 2misc */
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int pass;
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/* Coverity claims (size == 3 && !is_q) has been eliminated
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* from all paths leading to here.
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*/
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tcg_debug_assert(is_q);
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for (pass = 0; pass < 2; pass++) {
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TCGv_i64 tcg_op = tcg_temp_new_i64();
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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read_vec_element(s, tcg_op, rn, pass, MO_64);
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handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
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tcg_rmode, tcg_fpstatus);
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write_vec_element(s, tcg_res, rd, pass, MO_64);
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}
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} else {
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{
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int pass;
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assert(size == 2);
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@ -9903,22 +9852,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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{
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/* Special cases for 32 bit elements */
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switch (opcode) {
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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gen_helper_vfp_tosls(tcg_res, tcg_op,
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tcg_constant_i32(0), tcg_fpstatus);
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break;
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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gen_helper_vfp_touls(tcg_res, tcg_op,
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tcg_constant_i32(0), tcg_fpstatus);
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break;
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case 0x7c: /* URSQRTE */
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gen_helper_rsqrte_u32(tcg_res, tcg_op);
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break;
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@ -9938,6 +9871,16 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
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case 0x5e: /* FRINT32X */
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case 0x1f: /* FRINT64Z */
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case 0x5f: /* FRINT64X */
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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g_assert_not_reached();
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}
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}
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@ -10006,36 +9949,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x3d: /* FRECPE */
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case 0x3f: /* FRECPX */
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break;
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case 0x1a: /* FCVTNS */
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rmode = FPROUNDING_TIEEVEN;
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break;
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case 0x1b: /* FCVTMS */
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rmode = FPROUNDING_NEGINF;
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break;
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case 0x1c: /* FCVTAS */
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rmode = FPROUNDING_TIEAWAY;
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break;
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case 0x3a: /* FCVTPS */
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rmode = FPROUNDING_POSINF;
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break;
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case 0x3b: /* FCVTZS */
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rmode = FPROUNDING_ZERO;
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break;
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case 0x5a: /* FCVTNU */
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rmode = FPROUNDING_TIEEVEN;
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break;
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case 0x5b: /* FCVTMU */
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rmode = FPROUNDING_NEGINF;
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break;
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case 0x5c: /* FCVTAU */
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rmode = FPROUNDING_TIEAWAY;
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break;
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case 0x7a: /* FCVTPU */
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rmode = FPROUNDING_POSINF;
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break;
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case 0x7b: /* FCVTZU */
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rmode = FPROUNDING_ZERO;
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break;
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case 0x7d: /* FRSQRTE */
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break;
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default:
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@ -10051,6 +9964,16 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
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case 0x79: /* FRINTI */
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case 0x1d: /* SCVTF */
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case 0x5d: /* UCVTF */
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case 0x1a: /* FCVTNS */
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case 0x1b: /* FCVTMS */
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case 0x1c: /* FCVTAS */
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case 0x3a: /* FCVTPS */
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case 0x3b: /* FCVTZS */
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case 0x5a: /* FCVTNU */
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case 0x5b: /* FCVTMU */
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case 0x5c: /* FCVTAU */
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case 0x7a: /* FCVTPU */
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case 0x7b: /* FCVTZU */
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unallocated_encoding(s);
|
||||
return;
|
||||
}
|
||||
|
|
@ -10115,23 +10038,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
|
|||
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
|
||||
|
||||
switch (fpop) {
|
||||
case 0x1a: /* FCVTNS */
|
||||
case 0x1b: /* FCVTMS */
|
||||
case 0x1c: /* FCVTAS */
|
||||
case 0x3a: /* FCVTPS */
|
||||
case 0x3b: /* FCVTZS */
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||||
gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
|
||||
break;
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||||
case 0x3d: /* FRECPE */
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gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
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||||
break;
|
||||
case 0x5a: /* FCVTNU */
|
||||
case 0x5b: /* FCVTMU */
|
||||
case 0x5c: /* FCVTAU */
|
||||
case 0x7a: /* FCVTPU */
|
||||
case 0x7b: /* FCVTZU */
|
||||
gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
|
||||
break;
|
||||
case 0x7d: /* FRSQRTE */
|
||||
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
|
||||
break;
|
||||
|
|
@ -10146,6 +10055,16 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
|
|||
case 0x58: /* FRINTA */
|
||||
case 0x79: /* FRINTI */
|
||||
case 0x59: /* FRINTX */
|
||||
case 0x1a: /* FCVTNS */
|
||||
case 0x1b: /* FCVTMS */
|
||||
case 0x1c: /* FCVTAS */
|
||||
case 0x3a: /* FCVTPS */
|
||||
case 0x3b: /* FCVTZS */
|
||||
case 0x5a: /* FCVTNU */
|
||||
case 0x5b: /* FCVTMU */
|
||||
case 0x5c: /* FCVTAU */
|
||||
case 0x7a: /* FCVTPU */
|
||||
case 0x7b: /* FCVTZU */
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2537,6 +2537,8 @@ DO_VCVT_FIXED(gvec_vcvt_rz_hu, helper_vfp_touhh_round_to_zero, uint16_t)
|
|||
clear_tail(d, oprsz, simd_maxsz(desc)); \
|
||||
}
|
||||
|
||||
DO_VCVT_RMODE(gvec_vcvt_rm_sd, helper_vfp_tosqd, uint64_t)
|
||||
DO_VCVT_RMODE(gvec_vcvt_rm_ud, helper_vfp_touqd, uint64_t)
|
||||
DO_VCVT_RMODE(gvec_vcvt_rm_ss, helper_vfp_tosls, uint32_t)
|
||||
DO_VCVT_RMODE(gvec_vcvt_rm_us, helper_vfp_touls, uint32_t)
|
||||
DO_VCVT_RMODE(gvec_vcvt_rm_sh, helper_vfp_toshh, uint16_t)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue