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target/arm: Convert handle_rev to decodetree

Browse source 
This includes REV16, REV32, REV64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:10 -06:00 • committed by Peter Maydell
parent 38f9950c8e
commit 7c6bdcdaed
2 changed files with 10 additions and 74 deletions
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5
target/arm/tcg/a64.decode
View file

@ -73,6 +73,7 @@
@qrr_b . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=0
@qrr_h . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=1
@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
@ -1657,3 +1658,7 @@ CMGE0_v 0.10 1110 ..1 00000 10001 0 ..... ..... @qrr_e
CMEQ0_v 0.00 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLE0_v 0.10 1110 ..1 00000 10011 0 ..... ..... @qrr_e
CMLT0_v 0.00 1110 ..1 00000 10101 0 ..... ..... @qrr_e
REV16_v 0.00 1110 001 00000 00011 0 ..... ..... @qrr_b
REV32_v 0.10 1110 0.1 00000 00001 0 ..... ..... @qrr_bh
REV64_v 0.00 1110 ..1 00000 00001 0 ..... ..... @qrr_e

79
target/arm/tcg/translate-a64.c
View file

@ -8939,6 +8939,8 @@ TRANS(CMGE0_v, do_gvec_fn2, a, gen_gvec_cge0)
TRANS(CMLT0_v, do_gvec_fn2, a, gen_gvec_clt0)
TRANS(CMLE0_v, do_gvec_fn2, a, gen_gvec_cle0)
TRANS(CMEQ0_v, do_gvec_fn2, a, gen_gvec_ceq0)
TRANS(REV16_v, do_gvec_fn2, a, gen_gvec_rev16)
TRANS(REV32_v, do_gvec_fn2, a, gen_gvec_rev32)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
@ -8953,6 +8955,7 @@ static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
TRANS(REV64_v, do_gvec_fn2_bhs, a, gen_gvec_rev64)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
@ -9882,76 +9885,6 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
}
}
static void handle_rev(DisasContext *s, int opcode, bool u,
bool is_q, int size, int rn, int rd)
{
int op = (opcode << 1) | u;
int opsz = op + size;
int grp_size = 3 - opsz;
int dsize = is_q ? 128 : 64;
int i;
if (opsz >= 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
if (size == 0) {
/* Special case bytes, use bswap op on each group of elements */
int groups = dsize / (8 << grp_size);
for (i = 0; i < groups; i++) {
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
read_vec_element(s, tcg_tmp, rn, i, grp_size);
switch (grp_size) {
case MO_16:
tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
break;
case MO_32:
tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp, TCG_BSWAP_IZ);
break;
case MO_64:
tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
break;
default:
g_assert_not_reached();
}
write_vec_element(s, tcg_tmp, rd, i, grp_size);
}
clear_vec_high(s, is_q, rd);
} else {
int revmask = (1 << grp_size) - 1;
int esize = 8 << size;
int elements = dsize / esize;
TCGv_i64 tcg_rn = tcg_temp_new_i64();
TCGv_i64 tcg_rd[2];
for (i = 0; i < 2; i++) {
tcg_rd[i] = tcg_temp_new_i64();
tcg_gen_movi_i64(tcg_rd[i], 0);
}
for (i = 0; i < elements; i++) {
int e_rev = (i & 0xf) ^ revmask;
int w = (e_rev * esize) / 64;
int o = (e_rev * esize) % 64;
read_vec_element(s, tcg_rn, rn, i, size);
tcg_gen_deposit_i64(tcg_rd[w], tcg_rd[w], tcg_rn, o, esize);
}
for (i = 0; i < 2; i++) {
write_vec_element(s, tcg_rd[i], rd, i, MO_64);
}
clear_vec_high(s, true, rd);
}
}
static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
bool is_q, int size, int rn, int rd)
{
@ -10066,10 +9999,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x0: /* REV64, REV32 */
case 0x1: /* REV16 */
handle_rev(s, opcode, u, is_q, size, rn, rd);
return;
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
@ -10272,6 +10201,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
}
default:
case 0x0: /* REV64, REV32 */
case 0x1: /* REV16 */
case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
case 0x5: /* CNT, NOT, RBIT */