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target/arm: Convert FSQRT (vector) to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:22 -06:00 • committed by Peter Maydell
parent ea30b3522a
commit 73a6f0c245
2 changed files with 53 additions and 19 deletions
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3
target/arm/tcg/a64.decode
View file

@ -1694,3 +1694,6 @@ FABS_v 0.00 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
FNEG_v 0.10 1110 111 11000 11111 0 ..... ..... @qrr_h
FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
FSQRT_v 0.10 1110 111 11001 11111 0 ..... ..... @qrr_h
FSQRT_v 0.10 1110 1.1 00001 11111 0 ..... ..... @qrr_sd

69
target/arm/tcg/translate-a64.c
View file

@ -9164,6 +9164,51 @@ static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(FABS_v, do_fabs_fneg_v, a, gen_gvec_fabs)
TRANS(FNEG_v, do_fabs_fneg_v, a, gen_gvec_fneg)
static bool do_fp1_vector(DisasContext *s, arg_qrr_e *a,
const FPScalar1 *f, int rmode)
{
TCGv_i32 tcg_rmode = NULL;
TCGv_ptr fpst;
int check = fp_access_check_vector_hsd(s, a->q, a->esz);
if (check <= 0) {
return check == 0;
}
fpst = fpstatus_ptr(a->esz == MO_16 ? FPST_FPCR_F16 : FPST_FPCR);
if (rmode >= 0) {
tcg_rmode = gen_set_rmode(rmode, fpst);
}
if (a->esz == MO_64) {
TCGv_i64 t64 = tcg_temp_new_i64();
for (int pass = 0; pass < 2; ++pass) {
read_vec_element(s, t64, a->rn, pass, MO_64);
f->gen_d(t64, t64, fpst);
write_vec_element(s, t64, a->rd, pass, MO_64);
}
} else {
TCGv_i32 t32 = tcg_temp_new_i32();
void (*gen)(TCGv_i32, TCGv_i32, TCGv_ptr)
= (a->esz == MO_16 ? f->gen_h : f->gen_s);
for (int pass = 0, n = (a->q ? 16 : 8) >> a->esz; pass < n; ++pass) {
read_vec_element_i32(s, t32, a->rn, pass, a->esz);
gen(t32, t32, fpst);
write_vec_element_i32(s, t32, a->rd, pass, a->esz);
}
}
clear_vec_high(s, a->q, a->rd);
if (rmode >= 0) {
gen_restore_rmode(tcg_rmode, fpst);
}
return true;
}
TRANS(FSQRT_v, do_fp1_vector, a, &f_scalar_fsqrt, -1)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@ -9461,9 +9506,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* requires them.
*/
switch (opcode) {
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@ -9507,6 +9549,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0xb: /* ABS, NEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@ -10004,13 +10047,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
return;
case 0x7f: /* FSQRT */
need_fpstatus = true;
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x3a: /* FCVTPS */
@ -10104,6 +10140,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
unallocated_encoding(s);
return;
}
@ -10176,9 +10213,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x1a: /* FCVTNS */
case 0x1b: /* FCVTMS */
case 0x1c: /* FCVTAS */
@ -10221,6 +10255,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x7: /* SQABS, SQNEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
g_assert_not_reached();
}
}
@ -10365,12 +10400,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
break;
case 0x7d: /* FRSQRTE */
break;
case 0x7f: /* FSQRT (vector) */
only_in_vector = true;
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT (vector) */
unallocated_encoding(s);
return;
}
@ -10475,12 +10508,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
case 0x7f: /* FSQRT */
g_assert_not_reached();
}