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target/arm: Convert FABS, FNEG (vector) to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-55-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:21 -06:00 • committed by Peter Maydell
parent f0632d48a7
commit ea30b3522a
2 changed files with 31 additions and 30 deletions
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7
target/arm/tcg/a64.decode
View file

@ -77,6 +77,7 @@
@qrr_s . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=2
@qrr_bh . q:1 ...... . esz:1 ...... ...... rn:5 rd:5 &qrr_e
@qrr_hs . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_hs
@qrr_sd . q:1 ...... .. ...... ...... rn:5 rd:5 &qrr_e esz=%esz_sd
@qrr_e . q:1 ...... esz:2 ...... ...... rn:5 rd:5 &qrr_e
@qrrr_b . q:1 ...... ... rm:5 ...... rn:5 rd:5 &qrrr_e esz=0
@ -1687,3 +1688,9 @@ FCVTXN_v 0.10 1110 011 00001 01101 0 ..... ..... @qrr_s
BFCVTN_v 0.00 1110 101 00001 01101 0 ..... ..... @qrr_h
SHLL_v 0.10 1110 ..1 00001 00111 0 ..... ..... @qrr_e
FABS_v 0.00 1110 111 11000 11111 0 ..... ..... @qrr_h
FABS_v 0.00 1110 1.1 00000 11111 0 ..... ..... @qrr_sd
FNEG_v 0.10 1110 111 11000 11111 0 ..... ..... @qrr_h
FNEG_v 0.10 1110 1.1 00000 11111 0 ..... ..... @qrr_sd

54
target/arm/tcg/translate-a64.c
View file

@ -9149,6 +9149,20 @@ static bool trans_SHLL_v(DisasContext *s, arg_qrr_e *a)
return true;
}
static bool do_fabs_fneg_v(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
int check = fp_access_check_vector_hsd(s, a->q, a->esz);
if (check <= 0) {
return check == 0;
}
gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
return true;
}
TRANS(FABS_v, do_fabs_fneg_v, a, gen_gvec_fabs)
TRANS(FNEG_v, do_fabs_fneg_v, a, gen_gvec_fneg)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
@ -9447,12 +9461,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
* requires them.
*/
switch (opcode) {
case 0x2f: /* FABS */
gen_vfp_absd(tcg_rd, tcg_rn);
break;
case 0x6f: /* FNEG */
gen_vfp_negd(tcg_rd, tcg_rn);
break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_fpstatus);
break;
@ -9497,6 +9505,8 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
g_assert_not_reached();
}
}
@ -9968,13 +9978,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
size = is_double ? 3 : 2;
switch (opcode) {
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
if (size == 3 && !is_q) {
unallocated_encoding(s);
return;
}
break;
case 0x1d: /* SCVTF */
case 0x5d: /* UCVTF */
{
@ -10099,6 +10102,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x16: /* FCVTN, FCVTN2 */
case 0x36: /* BFCVTN, BFCVTN2 */
case 0x56: /* FCVTXN, FCVTXN2 */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
unallocated_encoding(s);
return;
}
@ -10171,12 +10176,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
{
/* Special cases for 32 bit elements */
switch (opcode) {
case 0x2f: /* FABS */
gen_vfp_abss(tcg_res, tcg_op);
break;
case 0x6f: /* FNEG */
gen_vfp_negs(tcg_res, tcg_op);
break;
case 0x7f: /* FSQRT */
gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_fpstatus);
break;
@ -10220,6 +10219,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
break;
default:
case 0x7: /* SQABS, SQNEG */
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
g_assert_not_reached();
}
}
@ -10362,17 +10363,14 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x7b: /* FCVTZU */
rmode = FPROUNDING_ZERO;
break;
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
only_in_vector = true;
need_fpst = false;
break;
case 0x7d: /* FRSQRTE */
break;
case 0x7f: /* FSQRT (vector) */
only_in_vector = true;
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
unallocated_encoding(s);
return;
}
@ -10474,12 +10472,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x59: /* FRINTX */
gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
break;
case 0x2f: /* FABS */
tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
break;
case 0x6f: /* FNEG */
tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
break;
case 0x7d: /* FRSQRTE */
gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
break;
@ -10487,6 +10479,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
gen_helper_vfp_sqrth(tcg_res, tcg_op, tcg_fpstatus);
break;
default:
case 0x2f: /* FABS */
case 0x6f: /* FNEG */
g_assert_not_reached();
}