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target/arm: Convert XTN, SQXTUN, SQXTN, UQXTN to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:16 -06:00 • committed by Peter Maydell
parent ace363a1e9
commit fbbc0b2c8a
2 changed files with 102 additions and 60 deletions
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9
target/arm/tcg/a64.decode
View file

@ -1642,6 +1642,10 @@ CMEQ0_s 0101 1110 111 00000 10011 0 ..... ..... @rr
CMLE0_s 0111 1110 111 00000 10011 0 ..... ..... @rr
CMLT0_s 0101 1110 111 00000 10101 0 ..... ..... @rr
SQXTUN_s 0111 1110 ..1 00001 00101 0 ..... ..... @rr_e
SQXTN_s 0101 1110 ..1 00001 01001 0 ..... ..... @rr_e
UQXTN_s 0111 1110 ..1 00001 01001 0 ..... ..... @rr_e
# Advanced SIMD two-register miscellaneous
SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
@ -1667,3 +1671,8 @@ SADDLP_v 0.00 1110 ..1 00000 00101 0 ..... ..... @qrr_e
UADDLP_v 0.10 1110 ..1 00000 00101 0 ..... ..... @qrr_e
SADALP_v 0.00 1110 ..1 00000 01101 0 ..... ..... @qrr_e
UADALP_v 0.10 1110 ..1 00000 01101 0 ..... ..... @qrr_e
XTN 0.00 1110 ..1 00001 00101 0 ..... ..... @qrr_e
SQXTUN_v 0.10 1110 ..1 00001 00101 0 ..... ..... @qrr_e
SQXTN_v 0.00 1110 ..1 00001 01001 0 ..... ..... @qrr_e
UQXTN_v 0.10 1110 ..1 00001 01001 0 ..... ..... @qrr_e

153
target/arm/tcg/translate-a64.c
View file

@ -8921,6 +8921,62 @@ TRANS(CMLE0_s, do_cmop0_d, a, TCG_COND_LE)
TRANS(CMLT0_s, do_cmop0_d, a, TCG_COND_LT)
TRANS(CMEQ0_s, do_cmop0_d, a, TCG_COND_EQ)
static bool do_2misc_narrow_scalar(DisasContext *s, arg_rr_e *a,
ArithOneOp * const fn[3])
{
if (a->esz == MO_64) {
return false;
}
if (fp_access_check(s)) {
TCGv_i64 t = tcg_temp_new_i64();
read_vec_element(s, t, a->rn, 0, a->esz + 1);
fn[a->esz](t, t);
clear_vec(s, a->rd);
write_vec_element(s, t, a->rd, 0, a->esz);
}
return true;
}
#define WRAP_ENV(NAME) \
static void gen_##NAME(TCGv_i64 d, TCGv_i64 n) \
{ gen_helper_##NAME(d, tcg_env, n); }
WRAP_ENV(neon_unarrow_sat8)
WRAP_ENV(neon_unarrow_sat16)
WRAP_ENV(neon_unarrow_sat32)
static ArithOneOp * const f_scalar_sqxtun[] = {
gen_neon_unarrow_sat8,
gen_neon_unarrow_sat16,
gen_neon_unarrow_sat32,
};
TRANS(SQXTUN_s, do_2misc_narrow_scalar, a, f_scalar_sqxtun)
WRAP_ENV(neon_narrow_sat_s8)
WRAP_ENV(neon_narrow_sat_s16)
WRAP_ENV(neon_narrow_sat_s32)
static ArithOneOp * const f_scalar_sqxtn[] = {
gen_neon_narrow_sat_s8,
gen_neon_narrow_sat_s16,
gen_neon_narrow_sat_s32,
};
TRANS(SQXTN_s, do_2misc_narrow_scalar, a, f_scalar_sqxtn)
WRAP_ENV(neon_narrow_sat_u8)
WRAP_ENV(neon_narrow_sat_u16)
WRAP_ENV(neon_narrow_sat_u32)
static ArithOneOp * const f_scalar_uqxtn[] = {
gen_neon_narrow_sat_u8,
gen_neon_narrow_sat_u16,
gen_neon_narrow_sat_u32,
};
TRANS(UQXTN_s, do_2misc_narrow_scalar, a, f_scalar_uqxtn)
#undef WRAP_ENV
static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
if (!a->q && a->esz == MO_64) {
@ -8964,6 +9020,37 @@ TRANS(UADDLP_v, do_gvec_fn2_bhs, a, gen_gvec_uaddlp)
TRANS(SADALP_v, do_gvec_fn2_bhs, a, gen_gvec_sadalp)
TRANS(UADALP_v, do_gvec_fn2_bhs, a, gen_gvec_uadalp)
static bool do_2misc_narrow_vector(DisasContext *s, arg_qrr_e *a,
ArithOneOp * const fn[3])
{
if (a->esz == MO_64) {
return false;
}
if (fp_access_check(s)) {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
read_vec_element(s, t0, a->rn, 0, MO_64);
read_vec_element(s, t1, a->rn, 1, MO_64);
fn[a->esz](t0, t0);
fn[a->esz](t1, t1);
write_vec_element(s, t0, a->rd, a->q ? 2 : 0, MO_32);
write_vec_element(s, t1, a->rd, a->q ? 3 : 1, MO_32);
clear_vec_high(s, a->q, a->rd);
}
return true;
}
static ArithOneOp * const f_scalar_xtn[] = {
gen_helper_neon_narrow_u8,
gen_helper_neon_narrow_u16,
tcg_gen_ext32u_i64,
};
TRANS(XTN, do_2misc_narrow_vector, a, f_scalar_xtn)
TRANS(SQXTUN_v, do_2misc_narrow_vector, a, f_scalar_sqxtun)
TRANS(SQXTN_v, do_2misc_narrow_vector, a, f_scalar_sqxtn)
TRANS(UQXTN_v, do_2misc_narrow_vector, a, f_scalar_uqxtn)
/* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed,
@ -9546,38 +9633,6 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
tcg_res[pass] = tcg_temp_new_i64();
switch (opcode) {
case 0x12: /* XTN, SQXTUN */
{
static NeonGenOne64OpFn * const xtnfns[3] = {
gen_helper_neon_narrow_u8,
gen_helper_neon_narrow_u16,
tcg_gen_ext32u_i64,
};
static NeonGenOne64OpEnvFn * const sqxtunfns[3] = {
gen_helper_neon_unarrow_sat8,
gen_helper_neon_unarrow_sat16,
gen_helper_neon_unarrow_sat32,
};
if (u) {
genenvfn = sqxtunfns[size];
} else {
genfn = xtnfns[size];
}
break;
}
case 0x14: /* SQXTN, UQXTN */
{
static NeonGenOne64OpEnvFn * const fns[3][2] = {
{ gen_helper_neon_narrow_sat_s8,
gen_helper_neon_narrow_sat_u8 },
{ gen_helper_neon_narrow_sat_s16,
gen_helper_neon_narrow_sat_u16 },
{ gen_helper_neon_narrow_sat_s32,
gen_helper_neon_narrow_sat_u32 },
};
genenvfn = fns[size][u];
break;
}
case 0x16: /* FCVTN, FCVTN2 */
/* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
if (size == 2) {
@ -9618,6 +9673,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
}
break;
default:
case 0x12: /* XTN, SQXTUN */
case 0x14: /* SQXTN, UQXTN */
g_assert_not_reached();
}
@ -9653,22 +9710,6 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x12: /* SQXTUN */
if (!u) {
unallocated_encoding(s);
return;
}
/* fall through */
case 0x14: /* SQXTN, UQXTN */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
return;
case 0xc ... 0xf:
case 0x16 ... 0x1d:
case 0x1f:
@ -9742,6 +9783,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
case 0x12: /* SQXTUN */
case 0x14: /* SQXTN, UQXTN */
unallocated_encoding(s);
return;
}
@ -9939,18 +9982,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
TCGv_ptr tcg_fpstatus;
switch (opcode) {
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
if (size == 3) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
return;
case 0x13: /* SHLL, SHLL2 */
if (u == 0 || size == 3) {
unallocated_encoding(s);
@ -10142,6 +10173,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0x9: /* CMEQ, CMLE */
case 0xa: /* CMLT */
case 0xb: /* ABS, NEG */
case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
unallocated_encoding(s);
return;
}