Chao Liu 4e9e2478df target/riscv: fix handling of nop for vstart >= vl in some vector instruction ... Recently, when I was writing a RISCV test, I found that when VL is set to 0, the instruction should be nop, but when I tested it, I found that QEMU will treat all elements as tail elements, and in the case of VTA=1, write all elements to 1. After troubleshooting, it was found that the vext_vx_rm_1 function was called in the vext_vx_rm_2, and then the vext_set_elems_1s function was called to process the tail element, but only VSTART >= vl was checked in the vext_vx_rm_1 function, which caused the tail element to still be processed even if it was returned in advance. So I've made the following change: Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function, so that the VSTART register is checked correctly. Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when vstart >= vl") Signed-off-by: Chao Liu <lc00631@tecorigin.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <b2649f14915150be4c602d63cd3ea4adf47e9d75.1741573286.git.lc00631@tecorigin.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2025-03-19 16:40:42 +10:00
..
insn_trans	target/riscv: fixes a bug against ssamoswap behavior in M-mode	2025-03-19 16:34:32 +10:00
kvm	accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'	2025-03-06 15:46:17 +01:00
tcg	accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h'	2025-03-06 15:46:17 +01:00
arch_dump.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu-param.h	target/*: Remove TARGET_LONG_BITS from cpu-param.h	2025-02-08 12:41:33 -08:00
cpu-qom.h	target/riscv: add RVA23S64 profile	2025-03-04 15:42:54 +10:00
cpu.c	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	2025-03-09 17:00:47 +01:00
cpu.h	target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL	2025-03-06 15:46:18 +01:00
cpu_bits.h	target/riscv: Fix the hpmevent mask	2025-03-04 15:42:54 +10:00
cpu_cfg.h	target/riscv/cpu.c: create flag for ziccrse	2025-03-04 15:42:54 +10:00
cpu_helper.c	exec: Declare tlb_set_page() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
cpu_user.h	target/riscv: zicfilp lpad impl and branch tracking	2024-10-30 11:22:08 +10:00
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()	2025-03-19 16:37:24 +10:00
debug.c	target/riscv/debug.c: use wp size = 4 for 32-bit CPUs	2025-03-04 15:42:54 +10:00
debug.h	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv/gdbstub: add V bit to priv reg	2025-01-19 09:44:34 +10:00
helper.h	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	2024-10-30 11:22:08 +10:00
insn32.decode	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	2025-03-09 17:00:47 +01:00
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	2024-10-02 15:11:51 +10:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: machine: Add Control Transfer Record state description	2025-03-04 15:42:54 +10:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
op_helper.c	exec: Declare tlb_flush*() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
pmp.c	exec: Declare tlb_flush*() in 'exec/cputlb.h'	2025-03-08 07:56:14 -08:00
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	2025-01-19 09:44:34 +10:00
pmu.c	target/riscv: Mask out upper sscofpmf bits during validation	2025-03-04 15:42:54 +10:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	qapi: Move include/qapi/qmp/ to include/qobject/	2025-02-10 15:33:16 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c	target/riscv: Stop timer with infinite timecmp	2024-10-02 15:11:51 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events	target/riscv: add trace in riscv_raise_exception()	2025-01-19 09:44:34 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Add support to record CTR entries.	2025-03-04 15:42:54 +10:00
vcrypto_helper.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
vector_helper.c	target/riscv: fix handling of nop for vstart >= vl in some vector instruction	2025-03-19 16:40:42 +10:00
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00