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riscv/gdbstub: add V bit to priv reg

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This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.

Note that GDB may display `INVALID` tag for `priv` reg when V bit
is set, this doesn't affect actual access to the bit though.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <tencent_1993B55C24DE7979BF34B200F78287002907@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yanfeng Liu 2024-12-16 05:36:35 +08:00 • committed by Alistair Francis
parent d4ce7ef4b3
commit e9952b3631
1 changed files with 19 additions and 4 deletions
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23
target/riscv/gdbstub.c
View file

@ -213,7 +213,10 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return gdb_get_regl(buf, env->priv);
/* Per RiscV debug spec v1.0.0 rc4 */
target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0;
return gdb_get_regl(buf, env->priv | vbit);
#endif
}
return 0;
@ -226,10 +229,22 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->priv = ldtul_p(mem_buf) & 0x3;
if (env->priv == PRV_RESERVED) {
env->priv = PRV_S;
target_ulong new_priv = ldtul_p(mem_buf) & 0x3;
bool new_virt = 0;
if (new_priv == PRV_RESERVED) {
new_priv = PRV_S;
}
if (new_priv != PRV_M) {
new_virt = (ldtul_p(mem_buf) & BIT(2)) >> 2;
}
if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) {
riscv_cpu_swap_hypervisor_regs(env);
}
riscv_cpu_set_mode(env, new_priv, new_virt);
#endif
return sizeof(target_ulong);
}