motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-02 15:23:53 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Fix the hpmevent mask

Browse source 
As per the latest privilege specification v1.13[1], the sscofpmf
only reserves first 8 bits of hpmeventX. Update the corresponding
masks accordingly.

[1]https://github.com/riscv/riscv-isa-manual/issues/1578

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250206-pmu_minor_fixes-v2-1-1bb0f4aeb8b4@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2025-02-06 01:58:46 -08:00 • committed by Alistair Francis
parent 81819038d7
commit 59eaf15704
1 changed files with 2 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

5
target/riscv/cpu_bits.h
View file

@ -1078,9 +1078,8 @@ typedef enum CTRType {
MHPMEVENTH_BIT_VSINH | \
MHPMEVENTH_BIT_VUINH)
#define MHPMEVENT_SSCOF_MASK _ULL(0xFFFF000000000000)
#define MHPMEVENT_IDX_MASK 0xFFFFF
#define MHPMEVENT_SSCOF_RESVD 16
#define MHPMEVENT_SSCOF_MASK MAKE_64BIT_MASK(63, 56)
#define MHPMEVENT_IDX_MASK (~MHPMEVENT_SSCOF_MASK)
/* RISC-V-specific interrupt pending bits. */
#define CPU_INTERRUPT_RNMI CPU_INTERRUPT_TGT_EXT_0