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target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL

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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250210133134.90879-5-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-02-10 10:11:16 +01:00
parent 05769aae62
commit 3bbcc0f732
2 changed files with 2 additions and 2 deletions
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2
target/riscv/cpu.c
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@ -3056,7 +3056,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
mcc->misa_mxl_max = (RISCVMXL)(uintptr_t)data;
riscv_cpu_validate_misa_mxl(mcc);
}

2
target/riscv/cpu.h
View file

@ -539,7 +539,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
uint32_t misa_mxl_max; /* max mxl for this cpu */
RISCVMXL misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)