Philippe Mathieu-Daudé 12d1a768bd qom: Have class_init() take a const data argument ... Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>		2025-04-25 17:00:41 +02:00
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insn_trans	target/riscv: Add check for 16-bit aligned PC for different priv versions.	2025-03-19 17:11:46 +10:00
kvm	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
tcg	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
arch_dump.c	include: Rename sysemu/ -> system/	2024-12-20 17:44:56 +01:00
bitmanip_helper.c	codebase: prepare to remove cpu.h from exec/exec-all.h	2025-04-23 13:52:25 -07:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu-param.h	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	2025-04-23 15:07:32 -07:00
cpu-qom.h	target/riscv: add RVA23S64 profile	2025-03-04 15:42:54 +10:00
cpu.c	qom: Have class_init() take a const data argument	2025-04-25 17:00:41 +02:00
cpu.h	tcg: Declare TARGET_INSN_START_EXTRA_WORDS in 'cpu-param.h'	2025-04-23 15:07:32 -07:00
cpu_bits.h	target/riscv: Fix the hpmevent mask	2025-03-04 15:42:54 +10:00
cpu_cfg.h	target/riscv: Remove ifndef CONFIG_USER_ONLY from cpu_cfg.h	2025-04-23 14:08:44 -07:00
cpu_helper.c	exec/cpu-all: remove exec/target_page include	2025-04-23 15:04:57 -07:00
cpu_user.h	target/riscv: zicfilp lpad impl and branch tracking	2024-10-30 11:22:08 +10:00
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	include/exec: Split out icount.h	2025-04-23 14:08:44 -07:00
debug.c	Miscellaneous patches for 2025-04-24	2025-04-24 13:44:57 -04:00
debug.h	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv/gdbstub: add V bit to priv reg	2025-01-19 09:44:34 +10:00
helper.h	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	2024-10-30 11:22:08 +10:00
insn32.decode	target/riscv: Add CTR sctrclr instruction.	2025-03-04 15:42:54 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: Move has_work() from CPUClass to SysemuCPUOps	2025-03-09 17:00:47 +01:00
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	2024-10-02 15:11:51 +10:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	include/exec: Split out icount.h	2025-04-23 14:08:44 -07:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
op_helper.c	exec: Restrict 'cpu_ldst.h' to accel/tcg/	2025-04-23 15:07:32 -07:00
pmp.c	exec/cpu-all: remove exec/target_page include	2025-04-23 15:04:57 -07:00
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	2025-01-19 09:44:34 +10:00
pmu.c	include/exec: Split out icount.h	2025-04-23 14:08:44 -07:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	qapi: Move include/qapi/qmp/ to include/qobject/	2025-02-10 15:33:16 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c	target/riscv: Stop timer with infinite timecmp	2024-10-02 15:11:51 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events	target/riscv: add trace in riscv_raise_exception()	2025-01-19 09:44:34 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	exec/cpu-all: remove exec/target_page include	2025-04-23 15:04:57 -07:00
vcrypto_helper.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
vector_helper.c	exec: Restrict 'cpu_ldst.h' to accel/tcg/	2025-04-23 15:07:32 -07:00
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	2025-03-19 16:39:00 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
zce_helper.c	exec: Restrict 'cpu_ldst.h' to accel/tcg/	2025-04-23 15:07:32 -07:00