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target/riscv: Add check for 16-bit aligned PC for different priv versions.

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For privilege version 1.12 or newer, C always implies Zca. We can only
check ext_zca to allow 16-bit aligned PC addresses. For older privilege
versions, we only check C.

Signed-off-by: Yu-Ming Chang <yumin686@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <174184718265.10540.10120024221661781046-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Yu-Ming Chang 2025-03-13 14:07:58 +08:00 • committed by Alistair Francis
parent 1a010d22b7
commit ffe4db11f8
4 changed files with 27 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

12
target/riscv/cpu.h
View file

@ -765,6 +765,18 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
}
#endif
static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg,
target_long priv_ver,
uint32_t misa_ext)
{
/* In priv spec version 1.12 or newer, C always implies Zca */
if (priv_ver >= PRIV_VERSION_1_12_0) {
return cfg->ext_zca;
} else {
return misa_ext & RVC;
}
}
/*
* Encode LMUL to lmul as follows:
* LMUL vlmul lmul

8
target/riscv/insn_trans/trans_rvi.c.inc
View file

@ -151,7 +151,9 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
tcg_gen_ext32s_tl(target_pc, target_pc);
}
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr,
ctx->priv_ver,
ctx->misa_ext)) {
TCGv t0 = tcg_temp_new();
misaligned = gen_new_label();
@ -300,7 +302,9 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
gen_set_label(l); /* branch taken */
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca &&
if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr,
ctx->priv_ver,
ctx->misa_ext) &&
(a->imm & 0x3)) {
/* misaligned */
TCGv target_pc = tcg_temp_new();

8
target/riscv/op_helper.c
View file

@ -279,7 +279,9 @@ target_ulong helper_sret(CPURISCVState *env)
}
target_ulong retpc = env->sepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg,
env->priv_ver,
env->misa_ext) && (retpc & 0x3)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
@ -357,7 +359,9 @@ static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc,
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg,
env->priv_ver,
env->misa_ext) && (retpc & 0x3)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}

4
target/riscv/translate.c
View file

@ -606,7 +606,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
TCGv succ_pc = dest_gpr(ctx, rd);
/* check misaligned: */
if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) {
if (!riscv_cpu_allow_16bit_insn(ctx->cfg_ptr,
ctx->priv_ver,
ctx->misa_ext)) {
if ((imm & 0x3) != 0) {
TCGv target_pc = tcg_temp_new();
gen_pc_plus_diff(target_pc, ctx, imm);