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Stefan Hajnoczi 54e91d1523 QAPI patches patches for 2025-02-10 
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Merge tag 'pull-qapi-2025-02-10-v2' of https://repo.or.cz/qemu/armbru into staging

QAPI patches patches for 2025-02-10

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# gpg: Signature made Mon 10 Feb 2025 09:47:13 EST
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* tag 'pull-qapi-2025-02-10-v2' of https://repo.or.cz/qemu/armbru:
  qapi: expose all schema features to code
  qapi: rename 'special_features' to 'features'
  qapi: change 'unsigned special_features' to 'uint64_t features'
  qapi: cope with feature names containing a '-'
  qapi/ui: Fix documentation of upper bound value in InputMoveEvent
  qapi: fix colon in Since tag section
  qapi: Move and rename qapi/qmp/dispatch.h to qapi/qmp-registry.h
  qapi: Move include/qapi/qmp/ to include/qobject/

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-10 10:47:31 -05:00
..
insn_trans target/riscv: Add Smrnmi mnret instruction 2025-01-19 09:44:34 +10:00
kvm target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu 2025-01-19 09:44:35 +10:00
tcg target/riscv: Add Smdbltrp ISA extension enable switch 2025-01-19 09:44:35 +10:00
arch_dump.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu-param.h target/*: Remove TARGET_LONG_BITS from cpu-param.h 2025-02-08 12:41:33 -08:00
cpu-qom.h target/riscv: add support for RV64 Xiangshan Nanhu CPU 2024-12-20 11:22:47 +10:00
cpu.c target/riscv: Support Supm and Sspm as part of Zjpm v1.0 2025-01-19 09:44:35 +10:00
cpu.h target/riscv: Add Ssdbltrp CSRs handling 2025-01-19 09:44:35 +10:00
cpu_bits.h target/riscv: Add Smdbltrp CSRs handling 2025-01-19 09:44:35 +10:00
cpu_cfg.h target/riscv: Support Supm and Sspm as part of Zjpm v1.0 2025-01-19 09:44:35 +10:00
cpu_helper.c target/riscv: Implement Smdbltrp behavior 2025-01-19 09:44:35 +10:00
cpu_user.h target/riscv: zicfilp lpad impl and branch tracking 2024-10-30 11:22:08 +10:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
crypto_helper.c target/riscv: Use accelerated helper for AES64KS1I 2023-09-11 11:45:55 +10:00
csr.c target/riscv: Add Smdbltrp CSRs handling 2025-01-19 09:44:35 +10:00
debug.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
debug.h target/riscv: Add textra matching condition for the triggers 2024-10-02 15:11:51 +10:00
fpu_helper.c target/riscv: Fix froundnx.h nanbox check 2024-06-26 23:02:35 +10:00
gdbstub.c riscv/gdbstub: add V bit to priv reg 2025-01-19 09:44:34 +10:00
helper.h target/riscv: Add Smrnmi mnret instruction 2025-01-19 09:44:34 +10:00
insn16.decode target/riscv: compressed encodings for sspush and sspopchk 2024-10-30 11:22:08 +10:00
insn32.decode target/riscv: Add Smrnmi mnret instruction 2025-01-19 09:44:34 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Apply pointer masking for virtualized memory accesses 2025-01-19 09:44:34 +10:00
Kconfig target/riscv/cpu_helper: Fix linking problem with semihosting disabled 2024-10-02 15:11:51 +10:00
m128_helper.c target/helpers: Remove unnecessary 'qemu/main-loop.h' header 2023-08-31 19:47:43 +02:00
machine.c target/riscv: Add counter delegation definitions 2025-01-19 09:44:35 +10:00
meson.build riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
monitor.c target/riscv: remove break after g_assert_not_reached() 2024-09-24 13:53:35 +02:00
op_helper.c target/riscv: Implement Smdbltrp sret, mret and mnret behavior 2025-01-19 09:44:35 +10:00
pmp.c target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 2025-01-19 09:44:34 +10:00
pmp.h target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 2025-01-19 09:44:34 +10:00
pmu.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
pmu.h target/riscv: More accurately model priv mode filtering. 2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c qapi: Move include/qapi/qmp/ to include/qobject/ 2025-02-10 15:33:16 +01:00
sbi_ecall_interface.h target/riscv/kvm: implement SBI debug console (DBCN) calls 2024-06-03 11:12:11 +10:00
th_csr.c riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
time_helper.c target/riscv: Stop timer with infinite timecmp 2024-10-02 15:11:51 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: add trace in riscv_raise_exception() 2025-01-19 09:44:34 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Update address modify functions to take into account pointer masking 2025-01-19 09:44:34 +10:00
vcrypto_helper.c target/riscv/vector_helpers: do early exit when vstart >= vl 2024-03-22 15:20:02 +10:00
vector_helper.c target/riscv: Apply pointer masking for virtualized memory accesses 2025-01-19 09:44:34 +10:00
vector_internals.c target/riscv: Fix the element agnostic function problem 2024-06-03 11:12:12 +10:00
vector_internals.h target/riscv: Include missing headers in 'vector_internals.h' 2024-12-20 11:22:47 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c target/riscv: add support for Zcmt extension 2023-05-05 10:49:50 +10:00