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qemu/target/riscv
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Stefan Hajnoczi 98721058d6 * target/i386/kvm: Intel TDX support 
* target/i386/emulate: more lflags cleanups
 * meson: remove need for explicit listing of dependencies in hw_common_arch and
   target_common_arch
 * rust: small fixes
 * hpet: Reorganize register decoding to be more similar to Rust code
 * target/i386: fixes for AMD models
 * target/i386: new EPYC-Turin CPU model
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Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* target/i386/kvm: Intel TDX support
* target/i386/emulate: more lflags cleanups
* meson: remove need for explicit listing of dependencies in hw_common_arch and
  target_common_arch
* rust: small fixes
* hpet: Reorganize register decoding to be more similar to Rust code
* target/i386: fixes for AMD models
* target/i386: new EPYC-Turin CPU model

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# gpg: Signature made Thu 29 May 2025 03:05:00 EDT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits)
  target/i386/tcg/helper-tcg: fix file references in comments
  target/i386: Add support for EPYC-Turin model
  target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits
  target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX
  target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits
  target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits
  target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits
  rust: make declaration of dependent crates more consistent
  docs: Add TDX documentation
  i386/tdx: Validate phys_bits against host value
  i386/tdx: Make invtsc default on
  i386/tdx: Don't treat SYSCALL as unavailable
  i386/tdx: Fetch and validate CPUID of TD guest
  target/i386: Print CPUID subleaf info for unsupported feature
  i386: Remove unused parameter "uint32_t bit" in feature_word_description()
  i386/cgs: Introduce x86_confidential_guest_check_features()
  i386/tdx: Define supported KVM features for TDX
  i386/tdx: Add XFD to supported bit of TDX
  i386/tdx: Add supported CPUID bits relates to XFAM
  i386/tdx: Add supported CPUID bits related to TD Attributes
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30 11:41:07 -04:00
..
insn_trans target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions 2025-05-19 13:39:15 +10:00
kvm kvm: Introduce kvm_arch_pre_create_vcpu() 2025-05-28 19:01:40 +02:00
tcg target/riscv: Fill in TCGCPUOps.pointer_wrap 2025-05-28 08:08:48 +01:00
arch_dump.c include: Rename sysemu/ -> system/ 2024-12-20 17:44:56 +01:00
bitmanip_helper.c codebase: prepare to remove cpu.h from exec/exec-all.h 2025-04-23 13:52:25 -07:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu-param.h tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally 2025-04-23 15:07:32 -07:00
cpu-qom.h target/riscv: convert SiFive U models to RISCVCPUDef 2025-05-20 08:18:53 +02:00
cpu.c target/riscv: remove .instance_post_init 2025-05-20 08:18:53 +02:00
cpu.h target/riscv: generalize custom CSR functionality 2025-05-20 08:18:53 +02:00
cpu_bits.h target/riscv: Fix the hpmevent mask 2025-03-04 15:42:54 +10:00
cpu_cfg.h target/riscv: include default value in cpu_cfg_fields.h.inc 2025-05-20 08:18:53 +02:00
cpu_cfg_fields.h.inc target/riscv: include default value in cpu_cfg_fields.h.inc 2025-05-20 08:18:53 +02:00
cpu_helper.c target/riscv: fix endless translation loop on big endian systems 2025-05-19 13:34:11 +10:00
cpu_user.h target/riscv: zicfilp lpad impl and branch tracking 2024-10-30 11:22:08 +10:00
cpu_vendorid.h target/riscv: add Ventana's Veyron V1 CPU 2023-05-05 10:49:50 +10:00
crypto_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
csr.c target/riscv: generalize custom CSR functionality 2025-05-20 08:18:53 +02:00
debug.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
debug.h target/riscv: Add textra matching condition for the triggers 2024-10-02 15:11:51 +10:00
fpu_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
gdbstub.c target/riscv: store RISCVCPUDef struct directly in the class 2025-05-20 08:18:53 +02:00
helper.h target/riscv: Add CTR sctrclr instruction. 2025-03-04 15:42:54 +10:00
insn16.decode target/riscv: compressed encodings for sspush and sspopchk 2024-10-30 11:22:08 +10:00
insn32.decode target/riscv: Fix the rvv reserved encoding of unmasked instructions 2025-05-19 13:39:20 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: Move insn_len to internals.h 2025-05-19 13:39:29 +10:00
Kconfig target/riscv/cpu_helper: Fix linking problem with semihosting disabled 2024-10-02 15:11:51 +10:00
m128_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
machine.c target/riscv: store RISCVCPUDef struct directly in the class 2025-05-20 08:18:53 +02:00
meson.build riscv: thead: Add th.sxstatus CSR emulation 2024-06-03 11:12:12 +10:00
monitor.c target/riscv: remove break after g_assert_not_reached() 2024-09-24 13:53:35 +02:00
op_helper.c target/riscv: Pass ra to riscv_csrrw_i128 2025-05-19 13:39:29 +10:00
pmp.c target/riscv: pmp: remove redundant check in pmp_is_locked 2025-05-19 13:30:15 +10:00
pmp.h target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0 2025-01-19 09:44:34 +10:00
pmu.c include/exec: Split out icount.h 2025-04-23 14:08:44 -07:00
pmu.h target/riscv: More accurately model priv mode filtering. 2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c qapi: make most CPU commands unconditionally available 2025-05-28 18:55:50 +02:00
sbi_ecall_interface.h target/riscv/kvm: implement SBI debug console (DBCN) calls 2024-06-03 11:12:11 +10:00
th_csr.c target/riscv: generalize custom CSR functionality 2025-05-20 08:18:53 +02:00
time_helper.c target/riscv: Stop timer with infinite timecmp 2024-10-02 15:11:51 +10:00
time_helper.h target/riscv: Simplify type conversion for CPURISCVState 2023-05-05 10:49:49 +10:00
trace-events target/riscv: add trace in riscv_raise_exception() 2025-01-19 09:44:34 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: store RISCVCPUDef struct directly in the class 2025-05-20 08:18:53 +02:00
vcrypto_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00
vector_helper.c target/riscv: Fix vslidedown with rvv_ta_all_1s 2025-05-19 13:39:25 +10:00
vector_internals.c target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter 2025-03-19 16:39:00 +10:00
vector_internals.h target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter 2025-03-19 16:39:00 +10:00
xthead.decode RISC-V: Adding XTheadFmv ISA extension 2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00
zce_helper.c include: Remove 'exec/exec-all.h' 2025-04-30 12:45:05 -07:00