motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2026-01-28 11:50:37 -07:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: Fill in TCGCPUOps.pointer_wrap

Browse source 
Check 32 vs 64-bit and pointer masking state.

Cc: qemu-riscv@nongnu.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-05-04 10:59:39 -07:00
parent 4031eb4fac
commit 8024f00415
1 changed files with 26 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

26
target/riscv/tcg/tcg-cpu.c
View file

@ -237,6 +237,31 @@ static void riscv_restore_state_to_opc(CPUState *cs,
env->excp_uw2 = data[2];
}
#ifndef CONFIG_USER_ONLY
static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_idx,
vaddr result, vaddr base)
{
CPURISCVState *env = cpu_env(cs);
uint32_t pm_len;
bool pm_signext;
if (cpu_address_xl(env) == MXL_RV32) {
return (uint32_t)result;
}
pm_len = riscv_pm_get_pmlen(riscv_pm_get_pmm(env));
if (pm_len == 0) {
return result;
}
pm_signext = riscv_cpu_virt_mem_enabled(env);
if (pm_signext) {
return sextract64(result, 0, 64 - pm_len);
}
return extract64(result, 0, 64 - pm_len);
}
#endif
const TCGCPUOps riscv_tcg_ops = {
.mttcg_supported = true,
.guest_default_memory_order = 0,
@ -250,6 +275,7 @@ const TCGCPUOps riscv_tcg_ops = {
#ifndef CONFIG_USER_ONLY
.tlb_fill = riscv_cpu_tlb_fill,
.pointer_wrap = riscv_pointer_wrap,
.cpu_exec_interrupt = riscv_cpu_exec_interrupt,
.cpu_exec_halt = riscv_cpu_has_work,
.cpu_exec_reset = cpu_reset,