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insn_trans
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target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions
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2025-05-19 13:39:15 +10:00 |
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kvm
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target/riscv: add more RISCVCPUDef fields
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2025-05-20 08:18:53 +02:00 |
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tcg
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target/riscv: store RISCVCPUDef struct directly in the class
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2025-05-20 08:18:53 +02:00 |
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arch_dump.c
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include: Rename sysemu/ -> system/
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2024-12-20 17:44:56 +01:00 |
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bitmanip_helper.c
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codebase: prepare to remove cpu.h from exec/exec-all.h
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2025-04-23 13:52:25 -07:00 |
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common-semi-target.h
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semihosting: Split out common-semi-target.h
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2022-06-28 04:35:07 +05:30 |
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cpu-param.h
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tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
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2025-04-23 15:07:32 -07:00 |
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cpu-qom.h
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target/riscv: convert SiFive U models to RISCVCPUDef
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2025-05-20 08:18:53 +02:00 |
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cpu.c
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target/riscv: convert THead C906 to RISCVCPUDef
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2025-05-20 08:18:53 +02:00 |
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cpu.h
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target/riscv: generalize custom CSR functionality
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2025-05-20 08:18:53 +02:00 |
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cpu_bits.h
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target/riscv: Fix the hpmevent mask
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2025-03-04 15:42:54 +10:00 |
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cpu_cfg.h
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target/riscv: include default value in cpu_cfg_fields.h.inc
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2025-05-20 08:18:53 +02:00 |
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cpu_cfg_fields.h.inc
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target/riscv: include default value in cpu_cfg_fields.h.inc
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2025-05-20 08:18:53 +02:00 |
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cpu_helper.c
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target/riscv: fix endless translation loop on big endian systems
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2025-05-19 13:34:11 +10:00 |
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cpu_user.h
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target/riscv: zicfilp lpad impl and branch tracking
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2024-10-30 11:22:08 +10:00 |
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cpu_vendorid.h
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target/riscv: add Ventana's Veyron V1 CPU
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2023-05-05 10:49:50 +10:00 |
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crypto_helper.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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csr.c
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target/riscv: generalize custom CSR functionality
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2025-05-20 08:18:53 +02:00 |
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debug.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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debug.h
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target/riscv: Add textra matching condition for the triggers
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2024-10-02 15:11:51 +10:00 |
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fpu_helper.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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gdbstub.c
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target/riscv: store RISCVCPUDef struct directly in the class
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2025-05-20 08:18:53 +02:00 |
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helper.h
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target/riscv: Add CTR sctrclr instruction.
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2025-03-04 15:42:54 +10:00 |
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insn16.decode
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target/riscv: compressed encodings for sspush and sspopchk
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2024-10-30 11:22:08 +10:00 |
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insn32.decode
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target/riscv: Fix the rvv reserved encoding of unmasked instructions
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2025-05-19 13:39:20 +10:00 |
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instmap.h
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target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
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2022-09-07 09:18:32 +02:00 |
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internals.h
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target/riscv: Move insn_len to internals.h
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2025-05-19 13:39:29 +10:00 |
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Kconfig
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target/riscv/cpu_helper: Fix linking problem with semihosting disabled
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2024-10-02 15:11:51 +10:00 |
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m128_helper.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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machine.c
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target/riscv: store RISCVCPUDef struct directly in the class
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2025-05-20 08:18:53 +02:00 |
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meson.build
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riscv: thead: Add th.sxstatus CSR emulation
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2024-06-03 11:12:12 +10:00 |
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monitor.c
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target/riscv: remove break after g_assert_not_reached()
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2024-09-24 13:53:35 +02:00 |
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op_helper.c
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target/riscv: Pass ra to riscv_csrrw_i128
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2025-05-19 13:39:29 +10:00 |
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pmp.c
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target/riscv: pmp: remove redundant check in pmp_is_locked
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2025-05-19 13:30:15 +10:00 |
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pmp.h
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target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0
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2025-01-19 09:44:34 +10:00 |
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pmu.c
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include/exec: Split out icount.h
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2025-04-23 14:08:44 -07:00 |
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pmu.h
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target/riscv: More accurately model priv mode filtering.
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2024-07-18 12:08:45 +10:00 |
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riscv-qmp-cmds.c
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qapi: Move include/qapi/qmp/ to include/qobject/
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2025-02-10 15:33:16 +01:00 |
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sbi_ecall_interface.h
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target/riscv/kvm: implement SBI debug console (DBCN) calls
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2024-06-03 11:12:11 +10:00 |
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th_csr.c
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target/riscv: generalize custom CSR functionality
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2025-05-20 08:18:53 +02:00 |
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time_helper.c
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target/riscv: Stop timer with infinite timecmp
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2024-10-02 15:11:51 +10:00 |
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time_helper.h
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target/riscv: Simplify type conversion for CPURISCVState
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2023-05-05 10:49:49 +10:00 |
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trace-events
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target/riscv: add trace in riscv_raise_exception()
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2025-01-19 09:44:34 +10:00 |
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trace.h
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trace: switch position of headers to what Meson requires
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2020-08-21 06:18:24 -04:00 |
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translate.c
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target/riscv: store RISCVCPUDef struct directly in the class
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2025-05-20 08:18:53 +02:00 |
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vcrypto_helper.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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vector_helper.c
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target/riscv: Fix vslidedown with rvv_ta_all_1s
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2025-05-19 13:39:25 +10:00 |
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vector_internals.c
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target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
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2025-03-19 16:39:00 +10:00 |
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vector_internals.h
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target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
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2025-03-19 16:39:00 +10:00 |
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xthead.decode
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RISC-V: Adding XTheadFmv ISA extension
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2023-02-07 08:19:23 +10:00 |
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XVentanaCondOps.decode
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |
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zce_helper.c
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include: Remove 'exec/exec-all.h'
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2025-04-30 12:45:05 -07:00 |
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