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Second RISC-V PR for 10.1

Browse source 
* sstc extension fixes
 * Fix zama16b order in isa_edata_arr
 * Profile handling fixes
 * Extend PMP region up to 64
 * Remove capital 'Z' CPU properties
 * Add missing named features
 * Support atomic instruction fetch (Ziccif)
 * Add max_satp_mode from host cpu
 * Extend and configure PMP region count
 * Fix PPN field of Translation-reponse register
 * Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
 * Fix fcvt.s.bf16 NaN box checking
 * Avoid infinite delay of async xmit function
 * Device tree reg cleanups
 * Add Kunminghu CPU and platform
 * Fix missing exit TB flow for ldff_trans
 * Fix migration failure when aia is configured as aplic-imsic
 * Fix MEPC/SEPC bit masking for IALIGN
 * Add a property to set vill bit on reserved usage of vsetvli instruction
 * Add Svrsw60t59b extension support
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Merge tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu into staging

Second RISC-V PR for 10.1

* sstc extension fixes
* Fix zama16b order in isa_edata_arr
* Profile handling fixes
* Extend PMP region up to 64
* Remove capital 'Z' CPU properties
* Add missing named features
* Support atomic instruction fetch (Ziccif)
* Add max_satp_mode from host cpu
* Extend and configure PMP region count
* Fix PPN field of Translation-reponse register
* Use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE
* Fix fcvt.s.bf16 NaN box checking
* Avoid infinite delay of async xmit function
* Device tree reg cleanups
* Add Kunminghu CPU and platform
* Fix missing exit TB flow for ldff_trans
* Fix migration failure when aia is configured as aplic-imsic
* Fix MEPC/SEPC bit masking for IALIGN
* Add a property to set vill bit on reserved usage of vsetvli instruction
* Add Svrsw60t59b extension support

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# gpg: Signature made Fri 04 Jul 2025 07:11:26 EDT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20250704' of https://github.com/alistair23/qemu: (40 commits)
  target: riscv: Add Svrsw60t59b extension support
  target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction
  tests/tcg/riscv64: Add test for MEPC bit masking
  target/riscv: Fix MEPC/SEPC bit masking for IALIGN
  migration: Fix migration failure when aia is configured as aplic-imsic
  target/riscv: rvv: Fix missing exit TB flow for ldff_trans
  hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype
  target/riscv: Add BOSC's Xiangshan Kunminghu CPU
  hw/riscv/virt: Use setprop_sized_cells for pcie
  hw/riscv/virt: Use setprop_sized_cells for iommu
  hw/riscv/virt: Use setprop_sized_cells for rtc
  hw/riscv/virt: Use setprop_sized_cells for uart
  hw/riscv/virt: Use setprop_sized_cells for reset
  hw/riscv/virt: Use setprop_sized_cells for virtio
  hw/riscv/virt: Use setprop_sized_cells for plic
  hw/riscv/virt: Use setprop_sized_cells for aclint
  hw/riscv/virt: Use setprop_sized_cells for aplic
  hw/riscv/virt: Use setprop_sized_cells for memory
  hw/riscv/virt: Use setprop_sized_cells for clint
  hw/riscv/virt: Fix clint base address type
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-07-04 08:58:58 -04:00
commit e240f6cc25
39 changed files with 1151 additions and 212 deletions
Download patch file Download diff file Expand all files Collapse all files

7
MAINTAINERS
View file

@ -1701,6 +1701,13 @@ S: Maintained
F: hw/riscv/microblaze-v-generic.c
F: docs/system/riscv/microblaze-v-generic.rst
Xiangshan Kunminghu
M: Ran Wang <wangran@bosc.ac.cn>
S: Maintained
F: docs/system/riscv/xiangshan-kunminghu.rst
F: hw/riscv/xiangshan_kmh.c
F: include/hw/riscv/xiangshan_kmh.h
RX Machines
-----------
rx-gdbsim

1
configs/devices/riscv64-softmmu/default.mak
View file

@ -11,3 +11,4 @@
# CONFIG_RISCV_VIRT=n
# CONFIG_MICROCHIP_PFSOC=n
# CONFIG_SHAKTI_C=n
# CONFIG_XIANGSHAN_KUNMINGHU=n

39
docs/system/riscv/xiangshan-kunminghu.rst Normal file
View file

@ -0,0 +1,39 @@
BOSC Xiangshan Kunminghu FPGA prototype platform (``xiangshan-kunminghu``)
==========================================================================
The ``xiangshan-kunminghu`` machine is compatible with our FPGA prototype
platform.
XiangShan is an open-source high-performance RISC-V processor project.
The third generation processor is called Kunminghu. Kunminghu is a 64-bit
RV64GCBSUHV processor core. More information can be found in our Github
repository:
https://github.com/OpenXiangShan/XiangShan
Supported devices
-----------------
The ``xiangshan-kunminghu`` machine supports the following devices:
* Up to 16 xiangshan-kunminghu cores
* Core Local Interruptor (CLINT)
* Incoming MSI Controller (IMSIC)
* Advanced Platform-Level Interrupt Controller (APLIC)
* 1 UART
Boot options
------------
The ``xiangshan-kunminghu`` machine can start using the standard ``-bios``
functionality for loading the boot image. You need to compile and link
the firmware, kernel, and Device Tree (FDT) into a single binary file,
such as ``fw_payload.bin``.
Running
-------
Below is an example command line for running the ``xiangshan-kunminghu``
machine:
.. code-block:: bash
$ qemu-system-riscv64 -machine xiangshan-kunminghu \
-smp 16 -m 16G \
-bios path/to/opensbi/platform/generic/firmware/fw_payload.bin \
-nographic

1
docs/system/target-riscv.rst
View file

@ -71,6 +71,7 @@ undocumented; you can get a complete list by running
riscv/shakti-c
riscv/sifive_u
riscv/virt
riscv/xiangshan-kunminghu
RISC-V CPU firmware
-------------------

6
hw/char/sifive_uart.c
View file

@ -128,8 +128,10 @@ static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *buf,
s->txfifo |= SIFIVE_UART_TXFIFO_FULL;
}
timer_mod(s->fifo_trigger_handle, current_time +
TX_INTERRUPT_TRIGGER_DELAY_NS);
if (!timer_pending(s->fifo_trigger_handle)) {
timer_mod(s->fifo_trigger_handle, current_time +
TX_INTERRUPT_TRIGGER_DELAY_NS);
}
}
static uint64_t

5
hw/intc/riscv_aclint.c
View file

@ -28,6 +28,7 @@
#include "qemu/module.h"
#include "hw/sysbus.h"
#include "target/riscv/cpu.h"
#include "target/riscv/time_helper.h"
#include "hw/qdev-properties.h"
#include "hw/intc/riscv_aclint.h"
#include "qemu/timer.h"
@ -240,6 +241,10 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,
riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu),
mtimer->hartid_base + i,
mtimer->timecmp[i]);
riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
}
return;
}

12
hw/intc/riscv_aplic.c
View file

@ -962,10 +962,18 @@ static const Property riscv_aplic_properties[] = {
DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0),
};
static bool riscv_aplic_state_needed(void *opaque)
{
RISCVAPLICState *aplic = opaque;
return riscv_use_emulated_aplic(aplic->msimode);
}
static const VMStateDescription vmstate_riscv_aplic = {
.name = "riscv_aplic",
.version_id = 2,
.minimum_version_id = 2,
.version_id = 3,
.minimum_version_id = 3,
.needed = riscv_aplic_state_needed,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(domaincfg, RISCVAPLICState),
VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState),

10
hw/intc/riscv_imsic.c
View file

@ -398,10 +398,16 @@ static const Property riscv_imsic_properties[] = {
DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0),
};
static bool riscv_imsic_state_needed(void *opaque)
{
return !kvm_irqchip_in_kernel();
}
static const VMStateDescription vmstate_riscv_imsic = {
.name = "riscv_imsic",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.needed = riscv_imsic_state_needed,
.fields = (const VMStateField[]) {
VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState,
num_pages, 0,

9
hw/riscv/Kconfig
View file

@ -119,3 +119,12 @@ config SPIKE
select HTIF
select RISCV_ACLINT
select SIFIVE_PLIC
config XIANGSHAN_KUNMINGHU
bool
default y
depends on RISCV64
select RISCV_ACLINT
select RISCV_APLIC
select RISCV_IMSIC
select SERIAL_MM

1
hw/riscv/meson.build
View file

@ -13,5 +13,6 @@ riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))
riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files(
'riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c', 'riscv-iommu-hpm.c'))
riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c'))
riscv_ss.add(when: 'CONFIG_XIANGSHAN_KUNMINGHU', if_true: files('xiangshan_kmh.c'))
hw_arch += {'riscv': riscv_ss}

1
hw/riscv/riscv-iommu-bits.h
View file

@ -79,6 +79,7 @@ struct riscv_iommu_pq_record {
#define RISCV_IOMMU_CAP_SV39 BIT_ULL(9)
#define RISCV_IOMMU_CAP_SV48 BIT_ULL(10)
#define RISCV_IOMMU_CAP_SV57 BIT_ULL(11)
#define RISCV_IOMMU_CAP_SVRSW60T59B BIT_ULL(14)
#define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16)
#define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17)
#define RISCV_IOMMU_CAP_SV48X4 BIT_ULL(18)

9
hw/riscv/riscv-iommu.c
View file

@ -1935,11 +1935,7 @@ static void riscv_iommu_process_dbg(RISCVIOMMUState *s)
iova = RISCV_IOMMU_TR_RESPONSE_FAULT | (((uint64_t) fault) << 10);
} else {
iova = iotlb.translated_addr & ~iotlb.addr_mask;
iova >>= TARGET_PAGE_BITS;
iova &= RISCV_IOMMU_TR_RESPONSE_PPN;
/* We do not support superpages (> 4kbs) for now */
iova &= ~RISCV_IOMMU_TR_RESPONSE_S;
iova = set_field(0, RISCV_IOMMU_TR_RESPONSE_PPN, PPN_DOWN(iova));
}
riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_TR_RESPONSE, iova);
}
@ -2355,7 +2351,8 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)
}
if (s->enable_g_stage) {
s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 |
RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4;
RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4 |
RISCV_IOMMU_CAP_SVRSW60T59B;
}
if (s->hpm_cntrs > 0) {

66
hw/riscv/virt.c
View file

@ -311,8 +311,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
size = riscv_socket_mem_size(ms, socket);
mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr);
qemu_fdt_add_subnode(ms->fdt, mem_name);
qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_sized_cells(ms->fdt, mem_name, "reg", 2, addr, 2, size);
qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory");
riscv_socket_fdt_write_id(ms, mem_name, socket);
}
@ -324,7 +323,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
int cpu;
g_autofree char *clint_name = NULL;
g_autofree uint32_t *clint_cells = NULL;
unsigned long clint_addr;
hwaddr clint_addr;
MachineState *ms = MACHINE(s);
static const char * const clint_compat[2] = {
"sifive,clint0", "riscv,clint0"
@ -340,14 +339,14 @@ static void create_fdt_socket_clint(RISCVVirtState *s,
}
clint_addr = s->memmap[VIRT_CLINT].base +
(s->memmap[VIRT_CLINT].size * socket);
clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
s->memmap[VIRT_CLINT].size * socket;
clint_name = g_strdup_printf("/soc/clint@%"HWADDR_PRIx, clint_addr);
qemu_fdt_add_subnode(ms->fdt, clint_name);
qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible",
(char **)&clint_compat,
ARRAY_SIZE(clint_compat));
qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg",
0x0, clint_addr, 0x0, s->memmap[VIRT_CLINT].size);
qemu_fdt_setprop_sized_cells(ms->fdt, clint_name, "reg",
2, clint_addr, 2, s->memmap[VIRT_CLINT].size);
qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended",
clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
riscv_socket_fdt_write_id(ms, clint_name, socket);
@ -388,8 +387,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mswi");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, addr, 2, RISCV_ACLINT_SWI_SIZE);
qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mswi_cells, aclint_cells_size);
qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
@ -411,11 +410,11 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-mtimer");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
0x0, RISCV_ACLINT_DEFAULT_MTIME);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, addr + RISCV_ACLINT_DEFAULT_MTIME,
2, size - RISCV_ACLINT_DEFAULT_MTIME,
2, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
2, RISCV_ACLINT_DEFAULT_MTIME);
qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_mtimer_cells, aclint_cells_size);
riscv_socket_fdt_write_id(ms, name, socket);
@ -429,8 +428,8 @@ static void create_fdt_socket_aclint(RISCVVirtState *s,
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"riscv,aclint-sswi");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr, 0x0, s->memmap[VIRT_ACLINT_SSWI].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, addr, 2, s->memmap[VIRT_ACLINT_SSWI].size);
qemu_fdt_setprop(ms->fdt, name, "interrupts-extended",
aclint_sswi_cells, aclint_cells_size);
qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0);
@ -494,8 +493,8 @@ static void create_fdt_socket_plic(RISCVVirtState *s,
s->soc[socket].num_harts * sizeof(uint32_t) * 4);
}
qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg",
0x0, plic_addr, 0x0, s->memmap[VIRT_PLIC].size);
qemu_fdt_setprop_sized_cells(ms->fdt, plic_name, "reg",
2, plic_addr, 2, s->memmap[VIRT_PLIC].size);
qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev",
VIRT_IRQCHIP_NUM_SOURCES - 1);
riscv_socket_fdt_write_id(ms, plic_name, socket);
@ -656,8 +655,8 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int socket,
qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phandle);
}
qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg",
0x0, aplic_addr, 0x0, aplic_size);
qemu_fdt_setprop_sized_cells(ms->fdt, aplic_name, "reg",
2, aplic_addr, 2, aplic_size);
qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources",
VIRT_IRQCHIP_NUM_SOURCES);
@ -857,9 +856,7 @@ static void create_fdt_virtio(RISCVVirtState *s, uint32_t irq_virtio_phandle)
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, addr,
0x0, size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, addr, 2, size);
qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_virtio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@ -897,8 +894,8 @@ static void create_fdt_pcie(RISCVVirtState *s,
if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle);
}
qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0,
s->memmap[VIRT_PCIE_ECAM].base, 0, s->memmap[VIRT_PCIE_ECAM].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2,
s->memmap[VIRT_PCIE_ECAM].base, 2, s->memmap[VIRT_PCIE_ECAM].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges",
1, FDT_PCI_RANGE_IOPORT, 2, 0,
2, s->memmap[VIRT_PCIE_PIO].base, 2, s->memmap[VIRT_PCIE_PIO].size,
@ -935,8 +932,9 @@ static void create_fdt_reset(RISCVVirtState *s, uint32_t *phandle)
qemu_fdt_setprop_string_array(ms->fdt, name, "compatible",
(char **)&compat, ARRAY_SIZE(compat));
}
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, s->memmap[VIRT_TEST].base, 0x0, s->memmap[VIRT_TEST].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, s->memmap[VIRT_TEST].base,
2, s->memmap[VIRT_TEST].size);
qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle);
test_phandle = qemu_fdt_get_phandle(ms->fdt, name);
g_free(name);
@ -968,9 +966,9 @@ static void create_fdt_uart(RISCVVirtState *s,
s->memmap[VIRT_UART0].base);
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, s->memmap[VIRT_UART0].base,
0x0, s->memmap[VIRT_UART0].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, s->memmap[VIRT_UART0].base,
2, s->memmap[VIRT_UART0].size);
qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400);
qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@ -994,8 +992,9 @@ static void create_fdt_rtc(RISCVVirtState *s,
qemu_fdt_add_subnode(ms->fdt, name);
qemu_fdt_setprop_string(ms->fdt, name, "compatible",
"google,goldfish-rtc");
qemu_fdt_setprop_cells(ms->fdt, name, "reg",
0x0, s->memmap[VIRT_RTC].base, 0x0, s->memmap[VIRT_RTC].size);
qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg",
2, s->memmap[VIRT_RTC].base,
2, s->memmap[VIRT_RTC].size);
qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent",
irq_mmio_phandle);
if (s->aia_type == VIRT_AIA_TYPE_NONE) {
@ -1089,8 +1088,7 @@ static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip,
qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1);
qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle);
qemu_fdt_setprop_cells(fdt, iommu_node, "reg",
addr >> 32, addr, size >> 32, size);
qemu_fdt_setprop_sized_cells(fdt, iommu_node, "reg", 2, addr, 2, size);
qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip);
qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts",

220
hw/riscv/xiangshan_kmh.c Normal file
View file

@ -0,0 +1,220 @@
/*
* QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
* FPGA prototype platform
*
* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
* SPDX-License-Identifier: GPL-2.0-or-later
*
* Provides a board compatible with the Xiangshan Kunminghu
* FPGA prototype platform:
*
* 0) UART (16550A)
* 1) CLINT (Core-Local Interruptor)
* 2) IMSIC (Incoming MSI Controller)
* 3) APLIC (Advanced Platform-Level Interrupt Controller)
*
* More information can be found in our Github repository:
* https://github.com/OpenXiangShan/XiangShan
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2 or later, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "system/address-spaces.h"
#include "hw/boards.h"
#include "hw/char/serial-mm.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/riscv_aplic.h"
#include "hw/intc/riscv_imsic.h"
#include "hw/qdev-properties.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/xiangshan_kmh.h"
#include "hw/riscv/riscv_hart.h"
#include "system/system.h"
static const MemMapEntry xiangshan_kmh_memmap[] = {
[XIANGSHAN_KMH_ROM] = { 0x1000, 0xF000 },
[XIANGSHAN_KMH_UART0] = { 0x310B0000, 0x10000 },
[XIANGSHAN_KMH_CLINT] = { 0x38000000, 0x10000 },
[XIANGSHAN_KMH_APLIC_M] = { 0x31100000, 0x4000 },
[XIANGSHAN_KMH_APLIC_S] = { 0x31120000, 0x4000 },
[XIANGSHAN_KMH_IMSIC_M] = { 0x3A800000, 0x10000 },
[XIANGSHAN_KMH_IMSIC_S] = { 0x3B000000, 0x80000 },
[XIANGSHAN_KMH_DRAM] = { 0x80000000, 0x0 },
};
static DeviceState *xiangshan_kmh_create_aia(uint32_t num_harts)
{
int i;
const MemMapEntry *memmap = xiangshan_kmh_memmap;
hwaddr addr = 0;
DeviceState *aplic_m = NULL;
/* M-level IMSICs */
addr = memmap[XIANGSHAN_KMH_IMSIC_M].base;
for (i = 0; i < num_harts; i++) {
riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), i, true,
1, XIANGSHAN_KMH_IMSIC_NUM_IDS);
}
/* S-level IMSICs */
addr = memmap[XIANGSHAN_KMH_IMSIC_S].base;
for (i = 0; i < num_harts; i++) {
riscv_imsic_create(addr +
i * IMSIC_HART_SIZE(XIANGSHAN_KMH_IMSIC_GUEST_BITS),
i, false, 1 + XIANGSHAN_KMH_IMSIC_GUEST_BITS,
XIANGSHAN_KMH_IMSIC_NUM_IDS);
}
/* M-level APLIC */
aplic_m = riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base,
memmap[XIANGSHAN_KMH_APLIC_M].size,
0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
1, true, true, NULL);
/* S-level APLIC */
riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base,
memmap[XIANGSHAN_KMH_APLIC_S].size,
0, 0, XIANGSHAN_KMH_APLIC_NUM_SOURCES,
1, true, false, aplic_m);
return aplic_m;
}
static void xiangshan_kmh_soc_realize(DeviceState *dev, Error **errp)
{
MachineState *ms = MACHINE(qdev_get_machine());
XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(dev);
const MemMapEntry *memmap = xiangshan_kmh_memmap;
MemoryRegion *system_memory = get_system_memory();
uint32_t num_harts = ms->smp.cpus;
qdev_prop_set_uint32(DEVICE(&s->cpus), "num-harts", num_harts);
qdev_prop_set_uint32(DEVICE(&s->cpus), "hartid-base", 0);
qdev_prop_set_string(DEVICE(&s->cpus), "cpu-type",
TYPE_RISCV_CPU_XIANGSHAN_KMH);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
/* AIA */
s->irqchip = xiangshan_kmh_create_aia(num_harts);
/* UART */
serial_mm_init(system_memory, memmap[XIANGSHAN_KMH_UART0].base, 2,
qdev_get_gpio_in(s->irqchip, XIANGSHAN_KMH_UART0_IRQ),
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* CLINT */
riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base,
0, num_harts, false);
riscv_aclint_mtimer_create(memmap[XIANGSHAN_KMH_CLINT].base +
RISCV_ACLINT_SWI_SIZE,
RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
0, num_harts, RISCV_ACLINT_DEFAULT_MTIMECMP,
RISCV_ACLINT_DEFAULT_MTIME,
XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ, true);
/* ROM */
memory_region_init_rom(&s->rom, OBJECT(dev), "xiangshan.kunminghu.rom",
memmap[XIANGSHAN_KMH_ROM].size, &error_fatal);
memory_region_add_subregion(system_memory,
memmap[XIANGSHAN_KMH_ROM].base, &s->rom);
}
static void xiangshan_kmh_soc_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = xiangshan_kmh_soc_realize;
dc->user_creatable = false;
}
static void xiangshan_kmh_soc_instance_init(Object *obj)
{
XiangshanKmhSoCState *s = XIANGSHAN_KMH_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
}
static const TypeInfo xiangshan_kmh_soc_info = {
.name = TYPE_XIANGSHAN_KMH_SOC,
.parent = TYPE_DEVICE,
.instance_size = sizeof(XiangshanKmhSoCState),
.instance_init = xiangshan_kmh_soc_instance_init,
.class_init = xiangshan_kmh_soc_class_init,
};
static void xiangshan_kmh_soc_register_types(void)
{
type_register_static(&xiangshan_kmh_soc_info);
}
type_init(xiangshan_kmh_soc_register_types)
static void xiangshan_kmh_machine_init(MachineState *machine)
{
XiangshanKmhState *s = XIANGSHAN_KMH_MACHINE(machine);
const MemMapEntry *memmap = xiangshan_kmh_memmap;
MemoryRegion *system_memory = get_system_memory();
hwaddr start_addr = memmap[XIANGSHAN_KMH_DRAM].base;
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc,
TYPE_XIANGSHAN_KMH_SOC);
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
/* Register RAM */
memory_region_add_subregion(system_memory,
memmap[XIANGSHAN_KMH_DRAM].base,
machine->ram);
/* ROM reset vector */
riscv_setup_rom_reset_vec(machine, &s->soc.cpus,
start_addr,
memmap[XIANGSHAN_KMH_ROM].base,
memmap[XIANGSHAN_KMH_ROM].size, 0, 0);
if (machine->firmware) {
riscv_load_firmware(machine->firmware, &start_addr, NULL);
}
/* Note: dtb has been integrated into firmware(OpenSBI) when compiling */
}
static void xiangshan_kmh_machine_class_init(ObjectClass *klass, const void *data)
{
MachineClass *mc = MACHINE_CLASS(klass);
static const char *const valid_cpu_types[] = {
TYPE_RISCV_CPU_XIANGSHAN_KMH,
NULL
};
mc->desc = "RISC-V Board compatible with the Xiangshan " \
"Kunminghu FPGA prototype platform";
mc->init = xiangshan_kmh_machine_init;
mc->max_cpus = XIANGSHAN_KMH_MAX_CPUS;
mc->default_cpu_type = TYPE_RISCV_CPU_XIANGSHAN_KMH;
mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "xiangshan.kunminghu.ram";
}
static const TypeInfo xiangshan_kmh_machine_info = {
.name = TYPE_XIANGSHAN_KMH_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(XiangshanKmhState),
.class_init = xiangshan_kmh_machine_class_init,
};
static void xiangshan_kmh_machine_register_types(void)
{
type_register_static(&xiangshan_kmh_machine_info);
}
type_init(xiangshan_kmh_machine_register_types)

68
include/hw/riscv/xiangshan_kmh.h Normal file
View file

@ -0,0 +1,68 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* QEMU RISC-V Board Compatible with the Xiangshan Kunminghu
* FPGA prototype platform
*
* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC)
*
*/
#ifndef HW_XIANGSHAN_KMH_H
#define HW_XIANGSHAN_KMH_H
#include "hw/boards.h"
#include "hw/riscv/riscv_hart.h"
#define XIANGSHAN_KMH_MAX_CPUS 16
typedef struct XiangshanKmhSoCState {
/*< private >*/
DeviceState parent_obj;
/*< public >*/
RISCVHartArrayState cpus;
DeviceState *irqchip;
MemoryRegion rom;
} XiangshanKmhSoCState;
#define TYPE_XIANGSHAN_KMH_SOC "xiangshan.kunminghu.soc"
DECLARE_INSTANCE_CHECKER(XiangshanKmhSoCState, XIANGSHAN_KMH_SOC,
TYPE_XIANGSHAN_KMH_SOC)
typedef struct XiangshanKmhState {
/*< private >*/
MachineState parent_obj;
/*< public >*/
XiangshanKmhSoCState soc;
} XiangshanKmhState;
#define TYPE_XIANGSHAN_KMH_MACHINE MACHINE_TYPE_NAME("xiangshan-kunminghu")
DECLARE_INSTANCE_CHECKER(XiangshanKmhState, XIANGSHAN_KMH_MACHINE,
TYPE_XIANGSHAN_KMH_MACHINE)
enum {
XIANGSHAN_KMH_ROM,
XIANGSHAN_KMH_UART0,
XIANGSHAN_KMH_CLINT,
XIANGSHAN_KMH_APLIC_M,
XIANGSHAN_KMH_APLIC_S,
XIANGSHAN_KMH_IMSIC_M,
XIANGSHAN_KMH_IMSIC_S,
XIANGSHAN_KMH_DRAM,
};
enum {
XIANGSHAN_KMH_UART0_IRQ = 10,
};
/* Indicating Timebase-freq (1MHZ) */
#define XIANGSHAN_KMH_CLINT_TIMEBASE_FREQ 1000000
#define XIANGSHAN_KMH_IMSIC_NUM_IDS 255
#define XIANGSHAN_KMH_IMSIC_NUM_GUESTS 7
#define XIANGSHAN_KMH_IMSIC_GUEST_BITS 3
#define XIANGSHAN_KMH_APLIC_NUM_SOURCES 96
#endif

1
target/riscv/cpu-qom.h
View file

@ -55,6 +55,7 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
#define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)

144
target/riscv/cpu.c
View file

@ -127,8 +127,8 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug),
ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha),
ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12),
@ -216,6 +217,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_13_0, ext_ssnpm),
ISA_EXT_DATA_ENTRY(sspm, PRIV_VERSION_1_13_0, ext_sspm),
ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen),
ISA_EXT_DATA_ENTRY(ssstrict, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
@ -228,6 +230,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
ISA_EXT_DATA_ENTRY(svrsw60t59b, PRIV_VERSION_1_13_0, ext_svrsw60t59b),
ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte),
ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
@ -1117,6 +1120,7 @@ static void riscv_cpu_init(Object *obj)
cpu->cfg.cbom_blocksize = 64;
cpu->cfg.cbop_blocksize = 64;
cpu->cfg.cboz_blocksize = 64;
cpu->cfg.pmp_regions = 16;
cpu->env.vext_ver = VEXT_VERSION_1_00_0;
cpu->cfg.max_satp_mode = -1;
@ -1282,6 +1286,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
MULTI_EXT_CFG_BOOL("svrsw60t59b", ext_svrsw60t59b, false),
MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
@ -1375,35 +1380,28 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
* 'Named features' is the name we give to extensions that we
* don't want to expose to users. They are either immutable
* (always enabled/disable) or they'll vary depending on
* the resulting CPU state. They have riscv,isa strings
* and priv_ver like regular extensions.
* the resulting CPU state.
*
* Some of them are always enabled depending on priv version
* of the CPU and are declared directly in isa_edata_arr[].
* The ones listed here have special checks during finalize()
* time and require their own flags like regular extensions.
* See riscv_cpu_update_named_features() for more info.
*/
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true),
MULTI_EXT_CFG_BOOL("sha", ext_sha, true),
/*
* 'ziccrse' has its own flag because the KVM driver
* wants to enable/disable it on its own accord.
*/
MULTI_EXT_CFG_BOOL("ziccrse", ext_ziccrse, true),
{ },
};
/* Deprecated entries marked for future removal */
const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
{ },
};
static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname,
Error **errp)
{
@ -1568,6 +1566,46 @@ static const PropertyInfo prop_pmp = {
.set = prop_pmp_set,
};
static void prop_num_pmp_regions_set(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(obj);
uint8_t value;
visit_type_uint8(v, name, &value, errp);
if (cpu->cfg.pmp_regions != value && riscv_cpu_is_vendor(obj)) {
cpu_set_prop_err(cpu, name, errp);
return;
}
if (cpu->env.priv_ver < PRIV_VERSION_1_12_0 && value > OLD_MAX_RISCV_PMPS) {
error_setg(errp, "Number of PMP regions exceeds maximum available");
return;
} else if (value > MAX_RISCV_PMPS) {
error_setg(errp, "Number of PMP regions exceeds maximum available");
return;
}
cpu_option_add_user_setting(name, value);
cpu->cfg.pmp_regions = value;
}
static void prop_num_pmp_regions_get(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
uint8_t value = RISCV_CPU(obj)->cfg.pmp_regions;
visit_type_uint8(v, name, &value, errp);
}
static const PropertyInfo prop_num_pmp_regions = {
.type = "uint8",
.description = "num-pmp-regions",
.get = prop_num_pmp_regions_get,
.set = prop_num_pmp_regions_set,
};
static int priv_spec_from_str(const char *priv_spec_str)
{
int priv_version = -1;
@ -2567,6 +2605,7 @@ static const Property riscv_cpu_properties[] = {
{.name = "mmu", .info = &prop_mmu},
{.name = "pmp", .info = &prop_pmp},
{.name = "num-pmp-regions", .info = &prop_num_pmp_regions},
{.name = "priv_spec", .info = &prop_priv_spec},
{.name = "vext_spec", .info = &prop_vext_spec},
@ -2595,6 +2634,7 @@ static const Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl, false),
DEFINE_PROP_BOOL("rvv_vsetvl_x0_vill", RISCVCPU, cfg.rvv_vsetvl_x0_vill, false),
/*
* write_misa() is marked as experimental for now so mark
@ -2937,7 +2977,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_MBARE,
.cfg.ext_zifencei = true,
.cfg.ext_zicsr = true,
.cfg.pmp = true
.cfg.pmp = true,
.cfg.pmp_regions = 8
),
DEFINE_ABSTRACT_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_U, TYPE_RISCV_VENDOR_CPU,
@ -2948,7 +2989,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.ext_zifencei = true,
.cfg.ext_zicsr = true,
.cfg.mmu = true,
.cfg.pmp = true
.cfg.pmp = true,
.cfg.pmp_regions = 8
),
#if defined(TARGET_RISCV32) || \
@ -3167,6 +3209,64 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.cfg.max_satp_mode = VM_1_10_SV39,
),
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_XIANGSHAN_KMH, TYPE_RISCV_VENDOR_CPU,
.misa_mxl_max = MXL_RV64,
.misa_ext = RVG | RVC | RVB | RVS | RVU | RVH | RVV,
.priv_spec = PRIV_VERSION_1_13_0,
/*
* The RISC-V Instruction Set Manual: Volume I
* Unprivileged Architecture
*/
.cfg.ext_zicntr = true,
.cfg.ext_zihpm = true,
.cfg.ext_zihintntl = true,
.cfg.ext_zihintpause = true,
.cfg.ext_zimop = true,
.cfg.ext_zcmop = true,
.cfg.ext_zicond = true,
.cfg.ext_zawrs = true,
.cfg.ext_zacas = true,
.cfg.ext_zfh = true,
.cfg.ext_zfa = true,
.cfg.ext_zcb = true,
.cfg.ext_zbc = true,
.cfg.ext_zvfh = true,
.cfg.ext_zkn = true,
.cfg.ext_zks = true,
.cfg.ext_zkt = true,
.cfg.ext_zvbb = true,
.cfg.ext_zvkt = true,
/*
* The RISC-V Instruction Set Manual: Volume II
* Privileged Architecture
*/
.cfg.ext_smstateen = true,
.cfg.ext_smcsrind = true,
.cfg.ext_sscsrind = true,
.cfg.ext_svnapot = true,
.cfg.ext_svpbmt = true,
.cfg.ext_svinval = true,
.cfg.ext_sstc = true,
.cfg.ext_sscofpmf = true,
.cfg.ext_ssdbltrp = true,
.cfg.ext_ssnpm = true,
.cfg.ext_smnpm = true,
.cfg.ext_smmpm = true,
.cfg.ext_sspm = true,
.cfg.ext_supm = true,
/* The RISC-V Advanced Interrupt Architecture */
.cfg.ext_smaia = true,
.cfg.ext_ssaia = true,
/* RVA23 Profiles */
.cfg.ext_zicbom = true,
.cfg.ext_zicbop = true,
.cfg.ext_zicboz = true,
.cfg.ext_svade = true,
.cfg.mmu = true,
.cfg.pmp = true,
.cfg.max_satp_mode = VM_1_10_SV48,
),
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU,
.cfg.max_satp_mode = VM_1_10_SV57,

19
target/riscv/cpu.h
View file

@ -82,7 +82,22 @@ typedef struct riscv_cpu_profile {
struct riscv_cpu_profile *s_parent;
const char *name;
uint32_t misa_ext;
/*
* The profile is enabled/disabled via command line or
* via cpu_init(). Enabling a profile will add all its
* mandatory extensions in the CPU during init().
*/
bool enabled;
/*
* The profile is present in the CPU, i.e. the current set of
* CPU extensions complies with it. A profile can be enabled
* and not present (e.g. the user disabled a mandatory extension)
* and the other way around (e.g. all mandatory extensions are
* present in a non-profile CPU).
*
* QMP uses this flag.
*/
bool present;
bool user_set;
int priv_spec;
int satp_mode;
@ -159,7 +174,8 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[];
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
#define MAX_RISCV_PMPS (64)
#define OLD_MAX_RISCV_PMPS (16)
#if !defined(CONFIG_USER_ONLY)
#include "pmp.h"
@ -936,7 +952,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
typedef struct isa_ext_data {
const char *name;

63
target/riscv/cpu_bits.h
View file

@ -372,6 +372,18 @@
#define CSR_PMPCFG1 0x3a1
#define CSR_PMPCFG2 0x3a2
#define CSR_PMPCFG3 0x3a3
#define CSR_PMPCFG4 0x3a4
#define CSR_PMPCFG5 0x3a5
#define CSR_PMPCFG6 0x3a6
#define CSR_PMPCFG7 0x3a7
#define CSR_PMPCFG8 0x3a8
#define CSR_PMPCFG9 0x3a9
#define CSR_PMPCFG10 0x3aa
#define CSR_PMPCFG11 0x3ab
#define CSR_PMPCFG12 0x3ac
#define CSR_PMPCFG13 0x3ad
#define CSR_PMPCFG14 0x3ae
#define CSR_PMPCFG15 0x3af
#define CSR_PMPADDR0 0x3b0
#define CSR_PMPADDR1 0x3b1
#define CSR_PMPADDR2 0x3b2
@ -388,6 +400,54 @@
#define CSR_PMPADDR13 0x3bd
#define CSR_PMPADDR14 0x3be
#define CSR_PMPADDR15 0x3bf
#define CSR_PMPADDR16 0x3c0
#define CSR_PMPADDR17 0x3c1
#define CSR_PMPADDR18 0x3c2
#define CSR_PMPADDR19 0x3c3
#define CSR_PMPADDR20 0x3c4
#define CSR_PMPADDR21 0x3c5
#define CSR_PMPADDR22 0x3c6
#define CSR_PMPADDR23 0x3c7
#define CSR_PMPADDR24 0x3c8
#define CSR_PMPADDR25 0x3c9
#define CSR_PMPADDR26 0x3ca
#define CSR_PMPADDR27 0x3cb
#define CSR_PMPADDR28 0x3cc
#define CSR_PMPADDR29 0x3cd
#define CSR_PMPADDR30 0x3ce
#define CSR_PMPADDR31 0x3cf
#define CSR_PMPADDR32 0x3d0
#define CSR_PMPADDR33 0x3d1
#define CSR_PMPADDR34 0x3d2
#define CSR_PMPADDR35 0x3d3
#define CSR_PMPADDR36 0x3d4
#define CSR_PMPADDR37 0x3d5
#define CSR_PMPADDR38 0x3d6
#define CSR_PMPADDR39 0x3d7
#define CSR_PMPADDR40 0x3d8
#define CSR_PMPADDR41 0x3d9
#define CSR_PMPADDR42 0x3da
#define CSR_PMPADDR43 0x3db
#define CSR_PMPADDR44 0x3dc
#define CSR_PMPADDR45 0x3dd
#define CSR_PMPADDR46 0x3de
#define CSR_PMPADDR47 0x3df
#define CSR_PMPADDR48 0x3e0
#define CSR_PMPADDR49 0x3e1
#define CSR_PMPADDR50 0x3e2
#define CSR_PMPADDR51 0x3e3
#define CSR_PMPADDR52 0x3e4
#define CSR_PMPADDR53 0x3e5
#define CSR_PMPADDR54 0x3e6
#define CSR_PMPADDR55 0x3e7
#define CSR_PMPADDR56 0x3e8
#define CSR_PMPADDR57 0x3e9
#define CSR_PMPADDR58 0x3ea
#define CSR_PMPADDR59 0x3eb
#define CSR_PMPADDR60 0x3ec
#define CSR_PMPADDR61 0x3ed
#define CSR_PMPADDR62 0x3ee
#define CSR_PMPADDR63 0x3ef
/* RNMI */
#define CSR_MNSCRATCH 0x740
@ -675,7 +735,8 @@ typedef enum {
#define PTE_SOFT 0x300 /* Reserved for Software */
#define PTE_PBMT 0x6000000000000000ULL /* Page-based memory types */
#define PTE_N 0x8000000000000000ULL /* NAPOT translation */
#define PTE_RESERVED 0x1FC0000000000000ULL /* Reserved bits */
#define PTE_RESERVED(svrsw60t59b) \
(svrsw60t59b ? 0x07C0000000000000ULL : 0x1FC0000000000000ULL) /* Reserved bits */
#define PTE_ATTR (PTE_N | PTE_PBMT) /* All attributes bits */
/* Page table PPN shift amount */

3
target/riscv/cpu_cfg_fields.h.inc
View file

@ -57,6 +57,7 @@ BOOL_FIELD(ext_svadu)
BOOL_FIELD(ext_svinval)
BOOL_FIELD(ext_svnapot)
BOOL_FIELD(ext_svpbmt)
BOOL_FIELD(ext_svrsw60t59b)
BOOL_FIELD(ext_svvptc)
BOOL_FIELD(ext_svukte)
BOOL_FIELD(ext_zdinx)
@ -114,6 +115,7 @@ BOOL_FIELD(ext_supm)
BOOL_FIELD(rvv_ta_all_1s)
BOOL_FIELD(rvv_ma_all_1s)
BOOL_FIELD(rvv_vl_half_avl)
BOOL_FIELD(rvv_vsetvl_x0_vill)
/* Named features */
BOOL_FIELD(ext_svade)
BOOL_FIELD(ext_zic64b)
@ -163,6 +165,7 @@ TYPED_FIELD(uint16_t, elen, 0)
TYPED_FIELD(uint16_t, cbom_blocksize, 0)
TYPED_FIELD(uint16_t, cbop_blocksize, 0)
TYPED_FIELD(uint16_t, cboz_blocksize, 0)
TYPED_FIELD(uint8_t, pmp_regions, 0)
TYPED_FIELD(int8_t, max_satp_mode, -1)

3
target/riscv/cpu_helper.c
View file

@ -1309,6 +1309,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
bool svade = riscv_cpu_cfg(env)->ext_svade;
bool svadu = riscv_cpu_cfg(env)->ext_svadu;
bool adue = svadu ? env->menvcfg & MENVCFG_ADUE : !svade;
bool svrsw60t59b = riscv_cpu_cfg(env)->ext_svrsw60t59b;
if (first_stage && two_stage && env->virt_enabled) {
pbmte = pbmte && (env->henvcfg & HENVCFG_PBMTE);
@ -1376,7 +1377,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (riscv_cpu_sxl(env) == MXL_RV32) {
ppn = pte >> PTE_PPN_SHIFT;
} else {
if (pte & PTE_RESERVED) {
if (pte & PTE_RESERVED(svrsw60t59b)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits set in PTE: "
"addr: 0x%" HWADDR_PRIx " pte: 0x" TARGET_FMT_lx "\n",
__func__, pte_addr, pte);

192
target/riscv/csr.c
View file

@ -738,7 +738,10 @@ static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno)
static RISCVException pmp(CPURISCVState *env, int csrno)
{
if (riscv_cpu_cfg(env)->pmp) {
if (csrno <= CSR_PMPCFG3) {
int max_pmpcfg = (env->priv_ver >= PRIV_VERSION_1_12_0) ?
+ CSR_PMPCFG15 : CSR_PMPCFG3;
if (csrno <= max_pmpcfg) {
uint32_t reg_index = csrno - CSR_PMPCFG0;
/* TODO: RV128 restriction check */
@ -3126,14 +3129,14 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
static RISCVException read_mepc(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->mepc;
*val = env->mepc & get_xepc_mask(env);
return RISCV_EXCP_NONE;
}
static RISCVException write_mepc(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
env->mepc = val;
env->mepc = val & get_xepc_mask(env);
return RISCV_EXCP_NONE;
}
@ -3181,6 +3184,7 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
MENVCFG_CBZE | MENVCFG_CDE;
bool stce_changed = false;
if (riscv_cpu_mxl(env) == MXL_RV64) {
mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
@ -3206,8 +3210,18 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
if ((val & MENVCFG_DTE) == 0) {
env->mstatus &= ~MSTATUS_SDT;
}
if (cfg->ext_sstc &&
((env->menvcfg & MENVCFG_STCE) != (val & MENVCFG_STCE))) {
stce_changed = true;
}
}
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
if (stce_changed) {
riscv_timer_stce_changed(env, true, !!(val & MENVCFG_STCE));
}
return write_henvcfg(env, CSR_HENVCFG, env->henvcfg, ra);
}
@ -3230,12 +3244,23 @@ static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
(cfg->ext_smcdeleg ? MENVCFG_CDE : 0) |
(cfg->ext_ssdbltrp ? MENVCFG_DTE : 0);
uint64_t valh = (uint64_t)val << 32;
bool stce_changed = false;
if (cfg->ext_sstc &&
((env->menvcfg & MENVCFG_STCE) != (valh & MENVCFG_STCE))) {
stce_changed = true;
}
if ((valh & MENVCFG_DTE) == 0) {
env->mstatus &= ~MSTATUS_SDT;
}
env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
if (stce_changed) {
riscv_timer_stce_changed(env, true, !!(valh & MENVCFG_STCE));
}
return write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32, ra);
}
@ -3313,8 +3338,10 @@ static RISCVException read_henvcfg(CPURISCVState *env, int csrno,
static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
RISCVException ret;
bool stce_changed = false;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
@ -3340,6 +3367,11 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
get_field(val, HENVCFG_PMM) != PMM_FIELD_RESERVED) {
mask |= HENVCFG_PMM;
}
if (cfg->ext_sstc &&
((env->henvcfg & HENVCFG_STCE) != (val & HENVCFG_STCE))) {
stce_changed = true;
}
}
env->henvcfg = val & mask;
@ -3347,6 +3379,10 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
env->vsstatus &= ~MSTATUS_SDT;
}
if (stce_changed) {
riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE));
}
return RISCV_EXCP_NONE;
}
@ -3368,19 +3404,32 @@ static RISCVException read_henvcfgh(CPURISCVState *env, int csrno,
static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
HENVCFG_ADUE | HENVCFG_DTE);
uint64_t valh = (uint64_t)val << 32;
RISCVException ret;
bool stce_changed = false;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
if (cfg->ext_sstc &&
((env->henvcfg & HENVCFG_STCE) != (valh & HENVCFG_STCE))) {
stce_changed = true;
}
env->henvcfg = (env->henvcfg & 0xFFFFFFFF) | (valh & mask);
if ((env->henvcfg & HENVCFG_DTE) == 0) {
env->vsstatus &= ~MSTATUS_SDT;
}
if (stce_changed) {
riscv_timer_stce_changed(env, false, !!(val & HENVCFG_STCE));
}
return RISCV_EXCP_NONE;
}
@ -3651,7 +3700,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,
if (riscv_cpu_cfg(env)->ext_sstc && (env->priv == PRV_M) &&
get_field(env->menvcfg, MENVCFG_STCE)) {
/* sstc extension forbids STIP & VSTIP to be writeable in mip */
mask = mask & ~(MIP_STIP | MIP_VSTIP);
/* STIP is not writable when menvcfg.STCE is enabled. */
mask = mask & ~MIP_STIP;
/* VSTIP is not writable when both [mh]envcfg.STCE are enabled. */
if (get_field(env->henvcfg, HENVCFG_STCE)) {
mask = mask & ~MIP_VSTIP;
}
}
if (mask) {
@ -4113,14 +4169,14 @@ static RISCVException write_sscratch(CPURISCVState *env, int csrno,
static RISCVException read_sepc(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->sepc;
*val = env->sepc & get_xepc_mask(env);
return RISCV_EXCP_NONE;
}
static RISCVException write_sepc(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
env->sepc = val;
env->sepc = val & get_xepc_mask(env);
return RISCV_EXCP_NONE;
}
@ -6111,6 +6167,30 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG3] = { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG4] = { "pmpcfg4", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG5] = { "pmpcfg5", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG6] = { "pmpcfg6", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG7] = { "pmpcfg7", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG8] = { "pmpcfg8", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG9] = { "pmpcfg9", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG10] = { "pmpcfg10", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG11] = { "pmpcfg11", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG12] = { "pmpcfg12", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG13] = { "pmpcfg13", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG14] = { "pmpcfg14", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPCFG15] = { "pmpcfg15", pmp, read_pmpcfg, write_pmpcfg,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR0] = { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR1] = { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR2] = { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr },
@ -6125,8 +6205,104 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR11] = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR12] = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR13] = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR16] = { "pmpaddr16", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR17] = { "pmpaddr17", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR18] = { "pmpaddr18", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR19] = { "pmpaddr19", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR20] = { "pmpaddr20", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR21] = { "pmpaddr21", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR22] = { "pmpaddr22", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR23] = { "pmpaddr23", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR24] = { "pmpaddr24", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR25] = { "pmpaddr25", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR26] = { "pmpaddr26", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR27] = { "pmpaddr27", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR28] = { "pmpaddr28", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR29] = { "pmpaddr29", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR30] = { "pmpaddr30", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR31] = { "pmpaddr31", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR32] = { "pmpaddr32", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR33] = { "pmpaddr33", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR34] = { "pmpaddr34", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR35] = { "pmpaddr35", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR36] = { "pmpaddr36", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR37] = { "pmpaddr37", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR38] = { "pmpaddr38", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR39] = { "pmpaddr39", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR40] = { "pmpaddr40", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR41] = { "pmpaddr41", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR42] = { "pmpaddr42", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR43] = { "pmpaddr43", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR44] = { "pmpaddr44", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR45] = { "pmpaddr45", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR46] = { "pmpaddr46", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR47] = { "pmpaddr47", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR48] = { "pmpaddr48", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR49] = { "pmpaddr49", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR50] = { "pmpaddr50", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR51] = { "pmpaddr51", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR52] = { "pmpaddr52", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR53] = { "pmpaddr53", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR54] = { "pmpaddr54", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR55] = { "pmpaddr55", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR56] = { "pmpaddr56", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR57] = { "pmpaddr57", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR58] = { "pmpaddr58", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR59] = { "pmpaddr59", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR60] = { "pmpaddr60", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR61] = { "pmpaddr61", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR62] = { "pmpaddr62", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
[CSR_PMPADDR63] = { "pmpaddr63", pmp, read_pmpaddr, write_pmpaddr,
.min_priv_ver = PRIV_VERSION_1_12_0 },
/* Debug CSRs */
[CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },

2
target/riscv/fpu_helper.c
View file

@ -755,6 +755,6 @@ uint64_t helper_fcvt_bf16_s(CPURISCVState *env, uint64_t rs1)
uint64_t helper_fcvt_s_bf16(CPURISCVState *env, uint64_t rs1)
{
float16 frs1 = check_nanbox_h(env, rs1);
float16 frs1 = check_nanbox_bf16(env, rs1);
return nanbox_s(env, bfloat16_to_float32(frs1, &env->fp_status));
}

2
target/riscv/helper.h
View file

@ -159,7 +159,7 @@ DEF_HELPER_FLAGS_3(hyp_hsv_d, TCG_CALL_NO_WG, void, env, tl, tl)
#endif
/* Vector functions */
DEF_HELPER_3(vsetvl, tl, env, tl, tl)
DEF_HELPER_4(vsetvl, tl, env, tl, tl, tl)
DEF_HELPER_5(vle8_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle16_v, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(vle32_v, void, ptr, ptr, tl, env, i32)

10
target/riscv/insn_trans/trans_rvv.c.inc
View file

@ -202,7 +202,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
s1 = get_gpr(s, rs1, EXT_ZERO);
}
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_helper_vsetvl(dst, tcg_env, s1, s2, tcg_constant_tl((int) (rd == 0 && rs1 == 0)));
gen_set_gpr(s, rd, dst);
finalize_rvv_inst(s);
@ -222,7 +222,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
dst = dest_gpr(s, rd);
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_helper_vsetvl(dst, tcg_env, s1, s2, tcg_constant_tl(0));
gen_set_gpr(s, rd, dst);
finalize_rvv_inst(s);
gen_update_pc(s, s->cur_insn_len);
@ -1361,6 +1361,12 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
finalize_rvv_inst(s);
/* vector unit-stride fault-only-first load may modify vl CSR */
gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
return true;
}

27
target/riscv/internals.h
View file

@ -142,6 +142,33 @@ static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
}
}
static inline float16 check_nanbox_bf16(CPURISCVState *env, uint64_t f)
{
/* Disable nanbox check when enable zfinx */
if (env_archcpu(env)->cfg.ext_zfinx) {
return (uint16_t)f;
}
uint64_t mask = MAKE_64BIT_MASK(16, 48);
if (likely((f & mask) == mask)) {
return (uint16_t)f;
} else {
return 0x7FC0u; /* default qnan */
}
}
static inline target_ulong get_xepc_mask(CPURISCVState *env)
{
/* When IALIGN=32, both low bits must be zero.
* When IALIGN=16 (has C extension), only bit 0 must be zero. */
if (riscv_has_ext(env, RVC)) {
return ~(target_ulong)1;
} else {
return ~(target_ulong)3;
}
}
#ifndef CONFIG_USER_ONLY
/* Our implementation of SysemuCPUOps::has_work */
bool riscv_cpu_has_work(CPUState *cs);

18
target/riscv/kvm/kvm-cpu.c
View file

@ -999,6 +999,19 @@ static void kvm_riscv_destroy_scratch_vcpu(KVMScratchCPU *scratch)
close(scratch->kvmfd);
}
static void kvm_riscv_init_max_satp_mode(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
{
struct kvm_one_reg reg;
int ret;
reg.id = RISCV_CONFIG_REG(satp_mode);
reg.addr = (uint64_t)&cpu->cfg.max_satp_mode;
ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, &reg);
if (ret != 0) {
error_report("Unable to retrieve satp mode from host, error %d", ret);
}
}
static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
{
struct kvm_one_reg reg;
@ -1302,6 +1315,7 @@ static void riscv_init_kvm_registers(Object *cpu_obj)
kvm_riscv_init_machine_ids(cpu, &kvmcpu);
kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu);
kvm_riscv_init_cfg(cpu, &kvmcpu);
kvm_riscv_init_max_satp_mode(cpu, &kvmcpu);
kvm_riscv_destroy_scratch_vcpu(&kvmcpu);
}
@ -1605,7 +1619,7 @@ static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
break;
case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE:
ch = run->riscv_sbi.args[0];
ret = qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch));
ret = qemu_chr_fe_write_all(serial_hd(0)->be, &ch, sizeof(ch));
if (ret < 0) {
error_report("SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: error when "
@ -1985,7 +1999,7 @@ static bool kvm_cpu_realize(CPUState *cs, Error **errp)
}
}
return true;
return true;
}
void riscv_kvm_cpu_finalize_features(RISCVCPU *cpu, Error **errp)

3
target/riscv/machine.c
View file

@ -36,8 +36,9 @@ static int pmp_post_load(void *opaque, int version_id)
RISCVCPU *cpu = opaque;
CPURISCVState *env = &cpu->env;
int i;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
for (i = 0; i < pmp_regions; i++) {
pmp_update_rule_addr(env, i);
}
pmp_update_rule_nums(env);

4
target/riscv/op_helper.c
View file

@ -280,7 +280,7 @@ target_ulong helper_sret(CPURISCVState *env)
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->sepc;
target_ulong retpc = env->sepc & get_xepc_mask(env);
if (!riscv_cpu_allow_16bit_insn(&env_archcpu(env)->cfg,
env->priv_ver,
env->misa_ext) && (retpc & 0x3)) {
@ -391,7 +391,7 @@ static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatus,
target_ulong helper_mret(CPURISCVState *env)
{
target_ulong retpc = env->mepc;
target_ulong retpc = env->mepc & get_xepc_mask(env);
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);

28
target/riscv/pmp.c
View file

@ -122,7 +122,9 @@ uint32_t pmp_get_num_rules(CPURISCVState *env)
*/
static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
{
if (pmp_index < MAX_RISCV_PMPS) {
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
if (pmp_index < pmp_regions) {
return env->pmp_state.pmp[pmp_index].cfg_reg;
}
@ -136,7 +138,9 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
*/
static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
if (pmp_index < pmp_regions) {
if (env->pmp_state.pmp[pmp_index].cfg_reg == val) {
/* no change */
return false;
@ -236,9 +240,10 @@ void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index)
void pmp_update_rule_nums(CPURISCVState *env)
{
int i;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
env->pmp_state.num_rules = 0;
for (i = 0; i < MAX_RISCV_PMPS; i++) {
for (i = 0; i < pmp_regions; i++) {
const uint8_t a_field =
pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg);
if (PMP_AMATCH_OFF != a_field) {
@ -332,6 +337,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
int pmp_size = 0;
hwaddr s = 0;
hwaddr e = 0;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
@ -356,7 +362,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, hwaddr addr,
* 1.10 draft priv spec states there is an implicit order
* from low to high
*/
for (i = 0; i < MAX_RISCV_PMPS; i++) {
for (i = 0; i < pmp_regions; i++) {
s = pmp_is_in_range(env, i, addr);
e = pmp_is_in_range(env, i, addr + pmp_size - 1);
@ -527,8 +533,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
{
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
bool is_next_cfg_tor = false;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
if (addr_index < MAX_RISCV_PMPS) {
if (addr_index < pmp_regions) {
if (env->pmp_state.pmp[addr_index].addr_reg == val) {
/* no change */
return;
@ -538,7 +545,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
* In TOR mode, need to check the lock bit of the next pmp
* (if there is a next).
*/
if (addr_index + 1 < MAX_RISCV_PMPS) {
if (addr_index + 1 < pmp_regions) {
uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg);
@ -573,8 +580,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
{
target_ulong val = 0;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
if (addr_index < MAX_RISCV_PMPS) {
if (addr_index < pmp_regions) {
val = env->pmp_state.pmp[addr_index].addr_reg;
trace_pmpaddr_csr_read(env->mhartid, addr_index, val);
} else {
@ -592,6 +600,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
{
int i;
uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
/* Update PMM field only if the value is valid according to Zjpm v1.0 */
if (riscv_cpu_cfg(env)->ext_smmpm &&
riscv_cpu_mxl(env) == MXL_RV64 &&
@ -603,7 +612,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
/* RLB cannot be enabled if it's already 0 and if any regions are locked */
if (!MSECCFG_RLB_ISSET(env)) {
for (i = 0; i < MAX_RISCV_PMPS; i++) {
for (i = 0; i < pmp_regions; i++) {
if (pmp_is_locked(env, i)) {
val &= ~MSECCFG_RLB;
break;
@ -659,6 +668,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
hwaddr tlb_sa = addr & ~(TARGET_PAGE_SIZE - 1);
hwaddr tlb_ea = tlb_sa + TARGET_PAGE_SIZE - 1;
int i;
uint8_t pmp_regions = riscv_cpu_cfg(env)->pmp_regions;
/*
* If PMP is not supported or there are no PMP rules, the TLB page will not
@ -669,7 +679,7 @@ target_ulong pmp_get_tlb_size(CPURISCVState *env, hwaddr addr)
return TARGET_PAGE_SIZE;
}
for (i = 0; i < MAX_RISCV_PMPS; i++) {
for (i = 0; i < pmp_regions; i++) {
if (pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg) == PMP_AMATCH_OFF) {
continue;
}

2
target/riscv/riscv-qmp-cmds.c
View file

@ -121,7 +121,7 @@ static void riscv_obj_add_profiles_qdict(Object *obj, QDict *qdict_out)
for (int i = 0; riscv_profiles[i] != NULL; i++) {
profile = riscv_profiles[i];
value = QOBJECT(qbool_from_bool(profile->enabled));
value = QOBJECT(qbool_from_bool(profile->present));
qdict_put_obj(qdict_out, profile->name, value);
}

186
target/riscv/tcg/tcg-cpu.c
View file

@ -451,6 +451,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
continue;
}
/*
* cpu.debug = true is marked as 'sdtrig', priv spec 1.12.
* Skip this warning since existing CPUs with older priv
* spec and debug = true will be impacted.
*/
if (!strcmp(edata->name, "sdtrig")) {
continue;
}
isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
/*
@ -830,6 +839,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_ssctr = false;
}
if (cpu->cfg.ext_svrsw60t59b &&
(!cpu->cfg.mmu || mcc->def->misa_mxl_max == MXL_RV32)) {
error_setg(errp, "svrsw60t59b is not supported on RV32 and MMU-less platforms");
return;
}
/*
* Disable isa extensions based on priv spec after we
* validated and set everything we need.
@ -867,16 +882,11 @@ static void riscv_cpu_check_parent_profile(RISCVCPU *cpu,
RISCVCPUProfile *profile,
RISCVCPUProfile *parent)
{
const char *parent_name;
bool parent_enabled;
if (!profile->enabled || !parent) {
if (!profile->present || !parent) {
return;
}
parent_name = parent->name;
parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL);
profile->enabled = parent_enabled;
profile->present = parent->present;
}
static void riscv_cpu_validate_profile(RISCVCPU *cpu,
@ -937,7 +947,7 @@ static void riscv_cpu_validate_profile(RISCVCPU *cpu,
}
}
profile->enabled = profile_impl;
profile->present = profile_impl;
riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent);
riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent);
@ -1166,6 +1176,70 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
}
static void riscv_cpu_set_profile(RISCVCPU *cpu,
RISCVCPUProfile *profile,
bool enabled)
{
int i, ext_offset;
if (profile->u_parent != NULL) {
riscv_cpu_set_profile(cpu, profile->u_parent, enabled);
}
if (profile->s_parent != NULL) {
riscv_cpu_set_profile(cpu, profile->s_parent, enabled);
}
profile->enabled = enabled;
if (profile->enabled) {
cpu->env.priv_ver = profile->priv_spec;
#ifndef CONFIG_USER_ONLY
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
object_property_set_bool(OBJECT(cpu), "mmu", true, NULL);
const char *satp_prop = satp_mode_str(profile->satp_mode,
riscv_cpu_is_32bit(cpu));
object_property_set_bool(OBJECT(cpu), satp_prop, true, NULL);
}
#endif
}
for (i = 0; misa_bits[i] != 0; i++) {
uint32_t bit = misa_bits[i];
if (!(profile->misa_ext & bit)) {
continue;
}
if (bit == RVI && !profile->enabled) {
/*
* Disabling profiles will not disable the base
* ISA RV64I.
*/
continue;
}
cpu_misa_ext_add_user_opt(bit, profile->enabled);
riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
}
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
if (profile->enabled) {
if (cpu_cfg_offset_is_named_feat(ext_offset)) {
riscv_cpu_enable_named_feat(cpu, ext_offset);
}
cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset);
}
cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
}
}
/*
* We'll get here via the following path:
*
@ -1332,7 +1406,6 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
RISCVCPUProfile *profile = opaque;
RISCVCPU *cpu = RISCV_CPU(obj);
bool value;
int i, ext_offset;
if (riscv_cpu_is_vendor(obj)) {
error_setg(errp, "Profile %s is not available for vendor CPUs",
@ -1351,64 +1424,8 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
}
profile->user_set = true;
profile->enabled = value;
if (profile->u_parent != NULL) {
object_property_set_bool(obj, profile->u_parent->name,
profile->enabled, NULL);
}
if (profile->s_parent != NULL) {
object_property_set_bool(obj, profile->s_parent->name,
profile->enabled, NULL);
}
if (profile->enabled) {
cpu->env.priv_ver = profile->priv_spec;
}
#ifndef CONFIG_USER_ONLY
if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
object_property_set_bool(obj, "mmu", true, NULL);
const char *satp_prop = satp_mode_str(profile->satp_mode,
riscv_cpu_is_32bit(cpu));
object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
}
#endif
for (i = 0; misa_bits[i] != 0; i++) {
uint32_t bit = misa_bits[i];
if (!(profile->misa_ext & bit)) {
continue;
}
if (bit == RVI && !profile->enabled) {
/*
* Disabling profiles will not disable the base
* ISA RV64I.
*/
continue;
}
cpu_misa_ext_add_user_opt(bit, profile->enabled);
riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
}
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
if (profile->enabled) {
if (cpu_cfg_offset_is_named_feat(ext_offset)) {
riscv_cpu_enable_named_feat(cpu, ext_offset);
}
cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset);
}
cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
}
riscv_cpu_set_profile(cpu, profile, value);
}
static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
@ -1423,7 +1440,7 @@ static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
static void riscv_cpu_add_profiles(Object *cpu_obj)
{
for (int i = 0; riscv_profiles[i] != NULL; i++) {
const RISCVCPUProfile *profile = riscv_profiles[i];
RISCVCPUProfile *profile = riscv_profiles[i];
object_property_add(cpu_obj, profile->name, "bool",
cpu_get_profile, cpu_set_profile,
@ -1435,30 +1452,11 @@ static void riscv_cpu_add_profiles(Object *cpu_obj)
* case.
*/
if (profile->enabled) {
object_property_set_bool(cpu_obj, profile->name, true, NULL);
riscv_cpu_set_profile(RISCV_CPU(cpu_obj), profile, true);
}
}
}
static bool cpu_ext_is_deprecated(const char *ext_name)
{
return isupper(ext_name[0]);
}
/*
* String will be allocated in the heap. Caller is responsible
* for freeing it.
*/
static char *cpu_ext_to_lower(const char *ext_name)
{
char *ret = g_malloc0(strlen(ext_name) + 1);
strcpy(ret, ext_name);
ret[0] = tolower(ret[0]);
return ret;
}
static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@ -1471,13 +1469,6 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
return;
}
if (cpu_ext_is_deprecated(multi_ext_cfg->name)) {
g_autofree char *lower = cpu_ext_to_lower(multi_ext_cfg->name);
warn_report("CPU property '%s' is deprecated. Please use '%s' instead",
multi_ext_cfg->name, lower);
}
cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value);
prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
@ -1513,14 +1504,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj,
const RISCVCPUMultiExtConfig *multi_cfg)
{
bool generic_cpu = riscv_cpu_is_generic(cpu_obj);
bool deprecated_ext = cpu_ext_is_deprecated(multi_cfg->name);
object_property_add(cpu_obj, multi_cfg->name, "bool",
cpu_get_multi_ext_cfg,
cpu_set_multi_ext_cfg,
NULL, (void *)multi_cfg);
if (!generic_cpu || deprecated_ext) {
if (!generic_cpu) {
return;
}
@ -1563,8 +1553,6 @@ static void riscv_cpu_add_user_properties(Object *obj)
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
riscv_cpu_add_profiles(obj);
}
@ -1606,6 +1594,8 @@ static void riscv_init_max_cpu_extensions(Object *obj)
if (env->misa_mxl != MXL_RV32) {
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false);
} else {
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_svrsw60t59b), false);
}
/*

65
target/riscv/time_helper.c
View file

@ -46,8 +46,23 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
{
uint64_t diff, ns_diff, next;
RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
uint32_t timebase_freq = mtimer->timebase_freq;
uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
uint32_t timebase_freq;
uint64_t rtc_r;
if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn ||
!env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) {
/* S/VS Timer IRQ depends on sstc extension, rdtime_fn(), and STCE. */
return;
}
if (timer_irq == MIP_VSTIP &&
(!riscv_has_ext(env, RVH) || !get_field(env->henvcfg, HENVCFG_STCE))) {
/* VS Timer IRQ also depends on RVH and henvcfg.STCE. */
return;
}
timebase_freq = mtimer->timebase_freq;
rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
if (timecmp <= rtc_r) {
/*
@ -125,6 +140,52 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
timer_mod(timer, next);
}
/*
* When disabling xenvcfg.STCE, the S/VS Timer may be disabled at the same time.
* It is safe to call this function regardless of whether the timer has been
* deleted or not. timer_del() will do nothing if the timer has already
* been deleted.
*/
static void riscv_timer_disable_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint32_t timer_irq)
{
/* Disable S-mode Timer IRQ and HW-based STIP */
if ((timer_irq == MIP_STIP) && !get_field(env->menvcfg, MENVCFG_STCE)) {
riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0));
timer_del(timer);
return;
}
/* Disable VS-mode Timer IRQ and HW-based VSTIP */
if ((timer_irq == MIP_VSTIP) &&
(!get_field(env->menvcfg, MENVCFG_STCE) ||
!get_field(env->henvcfg, HENVCFG_STCE))) {
env->vstime_irq = 0;
riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0));
timer_del(timer);
return;
}
}
/* Enable or disable S/VS-mode Timer when xenvcfg.STCE is changed */
void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool enable)
{
if (enable) {
riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp,
env->htimedelta, MIP_VSTIP);
} else {
riscv_timer_disable_timecmp(env, env->vstimer, MIP_VSTIP);
}
if (is_m_mode) {
if (enable) {
riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP);
} else {
riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP);
}
}
}
void riscv_timer_init(RISCVCPU *cpu)
{
CPURISCVState *env;

1
target/riscv/time_helper.h
View file

@ -25,6 +25,7 @@
void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
uint64_t timecmp, uint64_t delta,
uint32_t timer_irq);
void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool enable);
void riscv_timer_init(RISCVCPU *cpu);
#endif

46
target/riscv/translate.c
View file

@ -1217,13 +1217,35 @@ const RISCVDecoder decoder_table[] = {
const size_t decoder_table_size = ARRAY_SIZE(decoder_table);
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
static void decode_opc(CPURISCVState *env, DisasContext *ctx)
{
uint32_t opcode;
bool pc_is_4byte_align = ((ctx->base.pc_next % 4) == 0);
ctx->virt_inst_excp = false;
ctx->cur_insn_len = insn_len(opcode);
if (pc_is_4byte_align) {
/*
* Load 4 bytes at once to make instruction fetch atomically.
*
* Note: When pc is 4-byte aligned, 4-byte instruction wouldn't be
* across pages. We could preload 4 bytes instruction no matter
* real one is 2 or 4 bytes. Instruction preload wouldn't trigger
* additional page fault.
*/
opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
} else {
/*
* For unaligned pc, instruction preload may trigger additional
* page fault so we only load 2 bytes here.
*/
opcode = (uint32_t) translator_lduw(env, &ctx->base, ctx->base.pc_next);
}
ctx->ol = ctx->xl;
ctx->cur_insn_len = insn_len((uint16_t)opcode);
/* Check for compressed insn */
if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
ctx->opcode = (uint16_t)opcode;
/*
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
@ -1233,15 +1255,17 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
return;
}
} else {
uint32_t opcode32 = opcode;
opcode32 = deposit32(opcode32, 16, 16,
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
if (!pc_is_4byte_align) {
/* Load last 2 bytes of instruction here */
opcode = deposit32(opcode, 16, 16,
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
}
ctx->opcode = opcode;
for (guint i = 0; i < ctx->decoders->len; ++i) {
riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i);
if (func(ctx, opcode32)) {
if (func(ctx, opcode)) {
return;
}
}
@ -1319,10 +1343,8 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu_env(cpu);
uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
decode_opc(env, ctx);
ctx->base.pc_next += ctx->cur_insn_len;
/*

12
target/riscv/vector_helper.c
View file

@ -35,7 +35,7 @@
#include <math.h>
target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
target_ulong s2)
target_ulong s2, target_ulong x0)
{
int vlmax, vl;
RISCVCPU *cpu = env_archcpu(env);
@ -83,6 +83,16 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
} else {
vl = vlmax;
}
if (cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl != vl)) {
/* only set vill bit. */
env->vill = 1;
env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;
}
env->vl = vl;
env->vtype = s2;
env->vstart = 0;

BIN
tests/data/acpi/riscv64/virt/RHCT
View file

Binary file not shown.

4
tests/tcg/riscv64/Makefile.softmmu-target
View file

@ -20,5 +20,9 @@ EXTRA_RUNS += run-issue1060
run-issue1060: issue1060
$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
EXTRA_RUNS += run-test-mepc-masking
run-test-mepc-masking: test-mepc-masking
$(call run-test, $<, $(QEMU) $(QEMU_OPTS)$<)
# We don't currently support the multiarch system tests
undefine MULTIARCH_TESTS

73
tests/tcg/riscv64/test-mepc-masking.S Normal file
View file

@ -0,0 +1,73 @@
/*
* Test for MEPC masking bug fix
*
* This test verifies that MEPC properly masks the lower bits according
* to the RISC-V specification when vectored mode bits from STVEC are
* written to MEPC.
*/
.option norvc
.text
.global _start
_start:
/* Set up machine trap vector */
lla t0, machine_trap_handler
csrw mtvec, t0
/* Set STVEC with vectored mode (mode bits = 01) */
li t0, 0x80004001
csrw stvec, t0
/* Clear medeleg to handle exceptions in M-mode */
csrw medeleg, zero
/* Trigger illegal instruction exception */
.word 0xffffffff
test_completed:
/* Exit with result in a0 */
/* a0 = 0: success (bits [1:0] were masked) */
/* a0 != 0: failure (some bits were not masked) */
j _exit
machine_trap_handler:
/* Check if illegal instruction (mcause = 2) */
csrr t0, mcause
li t1, 2
bne t0, t1, skip_test
/* Test: Copy STVEC (with mode bits) to MEPC */
csrr t0, stvec /* t0 = 0x80004001 */
csrw mepc, t0 /* Write to MEPC */
csrr t1, mepc /* Read back MEPC */
/* Check if bits [1:0] are masked (IALIGN=32 without RVC) */
andi a0, t1, 3 /* a0 = 0 if both bits masked correctly */
/* Set correct return address */
lla t0, test_completed
csrw mepc, t0
skip_test:
mret
/* Exit with semihosting */
_exit:
lla a1, semiargs
li t0, 0x20026 /* ADP_Stopped_ApplicationExit */
sd t0, 0(a1)
sd a0, 8(a1)
li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */
/* Semihosting call sequence */
.balign 16
slli zero, zero, 0x1f
ebreak
srai zero, zero, 0x7
j .
.data
.balign 8
semiargs:
.space 16