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a1f44e0c59
Add a regression test to verify that MEPC properly masks the lower bits when an address with mode bits is written to it, as required by the RISC-V Privileged Architecture specification. The test sets STVEC to an address with bit 0 set (vectored mode), triggers an illegal instruction exception, copies STVEC to MEPC in the trap handler, and verifies that MEPC masks bits [1:0] correctly for IALIGN=32. Without the fix, MEPC retains the mode bits (returns non-zero/FAIL). With the fix, MEPC clears bits [1:0] (returns 0/PASS). Signed-off-by: Charalampos Mitrodimas <charmitro@posteo.net> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250703182157.281320-3-charmitro@posteo.net> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
73 lines
1.5 KiB
ArmAsm
73 lines
1.5 KiB
ArmAsm
/*
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* Test for MEPC masking bug fix
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*
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* This test verifies that MEPC properly masks the lower bits according
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* to the RISC-V specification when vectored mode bits from STVEC are
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* written to MEPC.
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*/
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.option norvc
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.text
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.global _start
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_start:
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/* Set up machine trap vector */
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lla t0, machine_trap_handler
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csrw mtvec, t0
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/* Set STVEC with vectored mode (mode bits = 01) */
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li t0, 0x80004001
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csrw stvec, t0
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/* Clear medeleg to handle exceptions in M-mode */
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csrw medeleg, zero
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/* Trigger illegal instruction exception */
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.word 0xffffffff
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test_completed:
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/* Exit with result in a0 */
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/* a0 = 0: success (bits [1:0] were masked) */
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/* a0 != 0: failure (some bits were not masked) */
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j _exit
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machine_trap_handler:
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/* Check if illegal instruction (mcause = 2) */
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csrr t0, mcause
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li t1, 2
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bne t0, t1, skip_test
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/* Test: Copy STVEC (with mode bits) to MEPC */
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csrr t0, stvec /* t0 = 0x80004001 */
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csrw mepc, t0 /* Write to MEPC */
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csrr t1, mepc /* Read back MEPC */
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/* Check if bits [1:0] are masked (IALIGN=32 without RVC) */
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andi a0, t1, 3 /* a0 = 0 if both bits masked correctly */
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/* Set correct return address */
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lla t0, test_completed
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csrw mepc, t0
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skip_test:
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mret
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/* Exit with semihosting */
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_exit:
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lla a1, semiargs
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li t0, 0x20026 /* ADP_Stopped_ApplicationExit */
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sd t0, 0(a1)
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sd a0, 8(a1)
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li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */
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/* Semihosting call sequence */
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.balign 16
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slli zero, zero, 0x1f
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ebreak
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srai zero, zero, 0x7
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j .
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.data
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.balign 8
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semiargs:
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.space 16
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