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https://github.com/Motorhead1991/qemu.git
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dff5f51540
Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. Signed-off-by: Jim Shu <jim.shu@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250519143518.11086-5-jim.shu@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
31 lines
1.1 KiB
C
31 lines
1.1 KiB
C
/*
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* RISC-V timer header file.
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*
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* Copyright (c) 2022 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_TIME_HELPER_H
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#define RISCV_TIME_HELPER_H
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#include "cpu.h"
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#include "qemu/timer.h"
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void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
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uint64_t timecmp, uint64_t delta,
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uint32_t timer_irq);
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void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool enable);
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void riscv_timer_init(RISCVCPU *cpu);
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#endif
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