qemu/target
Helge Deller 6966e0ba1d target/hppa: Fix FPE exceptions
Implement FP exception register #1 (lower 32-bits of 64-bit fr[0]).
A proper implementation is necessary to allow the Linux kernel in
system mode and the qemu linux-user to send proper si_code values
on SIGFPE signal.

Always set the T-bit on taken exception, and merge over- and underflow
in system mode to just set overflow bit to mimic the behaviour I tested
on a physical machine.

The test program below can be used to verify correct behaviour. Note
that behaviour on SIGFPE may vary on different platforms. The program
should always detect the correct signal, but it may or may not be able
to sucessfully continue afterwards.

 #define _GNU_SOURCE
 #include <signal.h>
 #include <stdio.h>
 #include <fenv.h>
 #include <float.h>

 static void fpe_func(int sig, siginfo_t *i, void *v) {
    sigset_t set;
    sigemptyset(&set);
    sigaddset(&set, SIGFPE);
    sigprocmask(SIG_UNBLOCK, &set, NULL);
    printf("GOT signal %d with si_code %ld\n", sig, i->si_code);
 }

 int main(int argc, char *argv[]) {
    struct sigaction action = {
        .sa_sigaction = fpe_func,
        .sa_flags = SA_RESTART|SA_SIGINFO };
    sigaction(SIGFPE, &action, 0);
    feenableexcept(FE_OVERFLOW | FE_UNDERFLOW);
    double x = DBL_MIN;
    return printf("%lf\n", argc > 1
        ? 1.7976931348623158E308*1.7976931348623158E308
        : x / 10);
 }

Signed-off-by: Helge Deller <deller@gmx.de>
(cherry picked from commit ebd394948d)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2025-05-25 11:20:04 +03:00
..
alpha target/alpha: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
arm target/arm: Don't assert() for ISB/SB inside IT block 2025-05-08 10:22:21 +03:00
avr target/avr: Improve decode of LDS, STS 2025-04-24 10:30:44 +03:00
hexagon target/hexagon: Remove CPUClass:has_work() handler 2025-03-09 17:00:47 +01:00
hppa target/hppa: Fix FPE exceptions 2025-05-25 11:20:04 +03:00
i386 i386/hvf: Make CPUID_HT supported 2025-05-22 14:27:23 +03:00
loongarch target/loongarch: Fix the cpu unplug resource leak 2025-03-27 20:29:17 +08:00
m68k target/m68k: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
microblaze target/microblaze: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
mips target/mips: Fix MIPS16e translation 2025-04-29 10:03:15 +03:00
openrisc target/openrisc: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
ppc hw/core: Get default_cpu_type calling machine_class_default_cpu_type() 2025-04-29 10:01:21 +03:00
riscv target/riscv/kvm: do not read unavailable CSRs 2025-05-20 10:04:19 +03:00
rx target/rx: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
s390x target/s390x: Fix a typo in s390_cpu_class_init() 2025-03-27 08:59:35 +01:00
sh4 target/sh4: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
sparc target/sparc: Log unimplemented ASI load/store accesses 2025-03-31 21:32:43 +02:00
tricore target/tricore: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
xtensa target/xtensa: Move has_work() from CPUClass to SysemuCPUOps 2025-03-09 17:00:47 +01:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00