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target/sparc: Log unimplemented ASI load/store accesses

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When the cache-controller feature is not implemented,
log potential ASI access as unimplemented.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Clément Chigot <chigot@adacore.com>
Message-Id: <20250325123927.74939-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2025-03-25 13:10:33 +01:00
parent 070a500cc0
commit 8001d22b0c
1 changed files with 6 additions and 0 deletions
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6
target/sparc/ldst_helper.c
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@ -600,6 +600,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr,
case 0x0C: /* Leon3 Date Cache config */
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
ret = leon3_cache_control_ld(env, addr, size);
} else {
qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented"
" address, size: %d\n", addr, size);
}
break;
case 0x01c00a00: /* MXCC control register */
@ -816,6 +819,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 0x0C: /* Leon3 Date Cache config */
if (env->def.features & CPU_FEATURE_CACHE_CTRL) {
leon3_cache_control_st(env, addr, val, size);
} else {
qemu_log_mask(LOG_UNIMP, "0x" TARGET_FMT_lx ": unimplemented"
" address, size: %d\n", addr, size);
}
break;