qemu/target
Clément Léger 2d8e825928 target/riscv: Add Smdbltrp ISA extension enable switch
Add the switch to enable the Smdbltrp ISA extension and disable it for
the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double
trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid
taking a double trap. OpenSBI does not currently support it so disable
it for the max cpu to avoid breaking regression tests.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250116131539.2475785-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-01-19 09:44:35 +10:00
..
alpha accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
arm acpi/ghes: better name GHES memory error function 2025-01-15 13:07:10 -05:00
avr accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hexagon accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hppa target/hppa: Speed up hppa_is_pa20() 2025-01-13 17:16:04 +01:00
i386 i386/cpu: Set and track CPUID_EXT3_CMP_LEG in env->features[FEAT_8000_0001_ECX] 2025-01-10 23:34:45 +01:00
loongarch target/loongarch: Add page table walker support for debugger usage 2025-01-15 14:16:51 +08:00
m68k accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
microblaze accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
mips target: Replace DEVICE(object_new) -> qdev_new() 2025-01-13 17:06:35 +01:00
openrisc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
ppc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
riscv target/riscv: Add Smdbltrp ISA extension enable switch 2025-01-19 09:44:35 +10:00
rx accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
s390x hw/s390x: Remove the cpu_model_allowed flag and related code 2025-01-07 14:51:39 +01:00
sh4 accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
sparc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
tricore accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
xtensa target: Replace DEVICE(object_new) -> qdev_new() 2025-01-13 17:06:35 +01:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00