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accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core

Browse source 
Convert all targets simultaneously, as the gen_intermediate_code
function disappears from the target.  While there are possible
workarounds, they're larger than simply performing the conversion.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-21 16:50:26 +00:00
parent 59abfb444e
commit e4a8e093dc
62 changed files with 121 additions and 62 deletions
Download patch file Download diff file Expand all files Collapse all files

8
accel/tcg/cpu-exec.c
View file

@ -1088,11 +1088,13 @@ bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
if (!tcg_target_initialized) {
/* Check mandatory TCGCPUOps handlers */
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
#ifndef CONFIG_USER_ONLY
assert(cpu->cc->tcg_ops->cpu_exec_halt);
assert(cpu->cc->tcg_ops->cpu_exec_interrupt);
assert(tcg_ops->cpu_exec_halt);
assert(tcg_ops->cpu_exec_interrupt);
#endif /* !CONFIG_USER_ONLY */
cpu->cc->tcg_ops->initialize();
assert(tcg_ops->translate_code);
tcg_ops->initialize();
tcg_target_initialized = true;
}

8
accel/tcg/translate-all.c
View file

@ -276,8 +276,10 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
tcg_func_start(tcg_ctx);
tcg_ctx->cpu = env_cpu(env);
gen_intermediate_code(env_cpu(env), tb, max_insns, pc, host_pc);
CPUState *cs = env_cpu(env);
tcg_ctx->cpu = cs;
cs->cc->tcg_ops->translate_code(cs, tb, max_insns, pc, host_pc);
assert(tb->size != 0);
tcg_ctx->cpu = NULL;
*max_insns = tb->icount;
@ -364,7 +366,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
/*
* Overflow of code_gen_buffer, or the current slice of it.
*
* TODO: We don't need to re-do gen_intermediate_code, nor
* TODO: We don't need to re-do tcg_ops->translate_code, nor
* should we re-do the tcg optimization currently hidden
* inside tcg_gen_code. All that should be required is to
* flush the TBs, allocate a new TB, re-initialize it per

14
include/exec/translator.h
View file

@ -21,20 +21,6 @@
#include "qemu/bswap.h"
#include "exec/vaddr.h"
/**
* gen_intermediate_code
* @cpu: cpu context
* @tb: translation block
* @max_insns: max number of instructions to translate
* @pc: guest virtual program counter address
* @host_pc: host physical program counter address
*
* This function must be provided by the target, which should create
* the target-specific DisasContext, and then invoke translator_loop.
*/
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc);
/**
* DisasJumpType:
* @DISAS_NEXT: Next instruction in program order.

13
include/hw/core/tcg-cpu-ops.h
View file

@ -24,6 +24,19 @@ struct TCGCPUOps {
* Called when the first CPU is realized.
*/
void (*initialize)(void);
/**
* @translate_code: Translate guest instructions to TCGOps
* @cpu: cpu context
* @tb: translation block
* @max_insns: max number of instructions to translate
* @pc: guest virtual program counter address
* @host_pc: host physical program counter address
*
* This function must be provided by the target, which should create
* the target-specific DisasContext, and then invoke translator_loop.
*/
void (*translate_code)(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
/**
* @synchronize_from_tb: Synchronize state from a TCG #TranslationBlock
*

1
target/alpha/cpu.c
View file

@ -224,6 +224,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
static const TCGCPUOps alpha_tcg_ops = {
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,
.synchronize_from_tb = alpha_cpu_synchronize_from_tb,
.restore_state_to_opc = alpha_restore_state_to_opc,

2
target/alpha/cpu.h
View file

@ -431,6 +431,8 @@ enum {
};
void alpha_translate_init(void);
void alpha_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU

4
target/alpha/translate.c
View file

@ -2955,8 +2955,8 @@ static const TranslatorOps alpha_tr_ops = {
.tb_stop = alpha_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void alpha_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);

1
target/arm/cpu.c
View file

@ -2682,6 +2682,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,

2
target/arm/internals.h
View file

@ -357,6 +357,8 @@ void init_cpreg_list(ARMCPU *cpu);
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
void arm_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void arm_cpu_register_gdb_commands(ARMCPU *cpu);
void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *,

1
target/arm/tcg/cpu-v7m.c
View file

@ -234,6 +234,7 @@ static void cortex_m55_initfn(Object *obj)
static const TCGCPUOps arm_v7m_tcg_ops = {
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
.debug_excp_handler = arm_debug_excp_handler,
.restore_state_to_opc = arm_restore_state_to_opc,

5
target/arm/tcg/translate.c
View file

@ -8093,9 +8093,8 @@ static const TranslatorOps thumb_translator_ops = {
.tb_stop = arm_tr_tb_stop,
};
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void arm_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;

1
target/avr/cpu.c
View file

@ -207,6 +207,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
static const TCGCPUOps avr_tcg_ops = {
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
.restore_state_to_opc = avr_restore_state_to_opc,
.cpu_exec_interrupt = avr_cpu_exec_interrupt,

2
target/avr/cpu.h
View file

@ -183,6 +183,8 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
}
void avr_cpu_tcg_init(void);
void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
int cpu_avr_exec(CPUState *cpu);

6
target/avr/translate.c
View file

@ -2599,7 +2599,7 @@ static bool trans_WDR(DisasContext *ctx, arg_WDR *a)
*
* - translate()
* - canonicalize_skip()
* - gen_intermediate_code()
* - translate_code()
* - restore_state_to_opc()
*
*/
@ -2795,8 +2795,8 @@ static const TranslatorOps avr_tr_ops = {
.tb_stop = avr_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void avr_cpu_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc = { };
translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);

1
target/hexagon/cpu.c
View file

@ -325,6 +325,7 @@ static void hexagon_cpu_init(Object *obj)
static const TCGCPUOps hexagon_tcg_ops = {
.initialize = hexagon_translate_init,
.translate_code = hexagon_translate_code,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
.restore_state_to_opc = hexagon_restore_state_to_opc,
};

2
target/hexagon/cpu.h
View file

@ -150,6 +150,8 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#include "exec/cpu-all.h"

4
target/hexagon/translate.c
View file

@ -1026,8 +1026,8 @@ static const TranslatorOps hexagon_tr_ops = {
.tb_stop = hexagon_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void hexagon_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

1
target/hppa/cpu.c
View file

@ -223,6 +223,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
static const TCGCPUOps hppa_tcg_ops = {
.initialize = hppa_translate_init,
.translate_code = hppa_translate_code,
.synchronize_from_tb = hppa_cpu_synchronize_from_tb,
.restore_state_to_opc = hppa_restore_state_to_opc,

2
target/hppa/cpu.h
View file

@ -303,6 +303,8 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
}
void hppa_translate_init(void);
void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

4
target/hppa/translate.c
View file

@ -4869,8 +4869,8 @@ static const TranslatorOps hppa_tr_ops = {
#endif
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void hppa_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx = { };
translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);

2
target/i386/tcg/helper-tcg.h
View file

@ -59,6 +59,8 @@ static inline target_long lshift(target_long x, int n)
/* translate.c */
void tcg_x86_init(void);
void x86_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
/* excp_helper.c */
G_NORETURN void raise_exception(CPUX86State *env, int exception_index);

1
target/i386/tcg/tcg-cpu.c
View file

@ -109,6 +109,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
static const TCGCPUOps x86_tcg_ops = {
.initialize = tcg_x86_init,
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
.restore_state_to_opc = x86_restore_state_to_opc,
.cpu_exec_enter = x86_cpu_exec_enter,

5
target/i386/tcg/translate.c
View file

@ -3814,9 +3814,8 @@ static const TranslatorOps i386_tr_ops = {
.tb_stop = i386_tr_tb_stop,
};
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void x86_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;

1
target/loongarch/cpu.c
View file

@ -795,6 +795,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
static const TCGCPUOps loongarch_tcg_ops = {
.initialize = loongarch_translate_init,
.translate_code = loongarch_translate_code,
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
.restore_state_to_opc = loongarch_restore_state_to_opc,

2
target/loongarch/internals.h
View file

@ -17,6 +17,8 @@
#define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
void loongarch_translate_init(void);
void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void G_NORETURN do_raise_exception(CPULoongArchState *env,
uint32_t exception,

4
target/loongarch/tcg/translate.c
View file

@ -333,8 +333,8 @@ static const TranslatorOps loongarch_tr_ops = {
.tb_stop = loongarch_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void loongarch_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

1
target/m68k/cpu.c
View file

@ -551,6 +551,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
static const TCGCPUOps m68k_tcg_ops = {
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,
.restore_state_to_opc = m68k_restore_state_to_opc,
#ifndef CONFIG_USER_ONLY

2
target/m68k/cpu.h
View file

@ -193,6 +193,8 @@ int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void m68k_tcg_init(void);
void m68k_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void m68k_cpu_init_gdb(M68kCPU *cpu);
uint32_t cpu_m68k_get_ccr(CPUM68KState *env);
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t);

4
target/m68k/translate.c
View file

@ -6118,8 +6118,8 @@ static const TranslatorOps m68k_tr_ops = {
.tb_stop = m68k_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void m68k_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);

1
target/microblaze/cpu.c
View file

@ -423,6 +423,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
static const TCGCPUOps mb_tcg_ops = {
.initialize = mb_tcg_init,
.translate_code = mb_translate_code,
.synchronize_from_tb = mb_cpu_synchronize_from_tb,
.restore_state_to_opc = mb_restore_state_to_opc,

2
target/microblaze/cpu.h
View file

@ -398,6 +398,8 @@ static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
}
void mb_tcg_init(void);
void mb_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU

4
target/microblaze/translate.c
View file

@ -1779,8 +1779,8 @@ static const TranslatorOps mb_tr_ops = {
.tb_stop = mb_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void mb_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);

1
target/mips/cpu.c
View file

@ -547,6 +547,7 @@ static const Property mips_cpu_properties[] = {
#include "hw/core/tcg-cpu-ops.h"
static const TCGCPUOps mips_tcg_ops = {
.initialize = mips_tcg_init,
.translate_code = mips_translate_code,
.synchronize_from_tb = mips_cpu_synchronize_from_tb,
.restore_state_to_opc = mips_restore_state_to_opc,

2
target/mips/tcg/tcg-internal.h
View file

@ -16,6 +16,8 @@
#include "cpu.h"
void mips_tcg_init(void);
void mips_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
G_NORETURN void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,

4
target/mips/tcg/translate.c
View file

@ -15231,8 +15231,8 @@ static const TranslatorOps mips_tr_ops = {
.tb_stop = mips_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void mips_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

1
target/openrisc/cpu.c
View file

@ -236,6 +236,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
.translate_code = openrisc_translate_code,
.synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
.restore_state_to_opc = openrisc_restore_state_to_opc,

2
target/openrisc/cpu.h
View file

@ -301,6 +301,8 @@ void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#ifndef CONFIG_USER_ONLY

4
target/openrisc/translate.c
View file

@ -1646,8 +1646,8 @@ static const TranslatorOps openrisc_tr_ops = {
.tb_stop = openrisc_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void openrisc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

2
target/ppc/cpu.h
View file

@ -1581,6 +1581,8 @@ extern const VMStateDescription vmstate_ppc_cpu;
/*****************************************************************************/
void ppc_translate_init(void);
void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#if !defined(CONFIG_USER_ONLY)
void ppc_store_sdr1(CPUPPCState *env, target_ulong value);

1
target/ppc/cpu_init.c
View file

@ -7431,6 +7431,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = {
static const TCGCPUOps ppc_tcg_ops = {
.initialize = ppc_translate_init,
.translate_code = ppc_translate_code,
.restore_state_to_opc = ppc_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY

4
target/ppc/translate.c
View file

@ -6669,8 +6669,8 @@ static const TranslatorOps ppc_tr_ops = {
.tb_stop = ppc_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void ppc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

3
target/riscv/cpu.h
View file

@ -602,6 +602,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en);
void riscv_translate_init(void);
void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
G_NORETURN void riscv_raise_exception(CPURISCVState *env,
uint32_t exception, uintptr_t pc);

1
target/riscv/tcg/tcg-cpu.c
View file

@ -135,6 +135,7 @@ static void riscv_restore_state_to_opc(CPUState *cs,
static const TCGCPUOps riscv_tcg_ops = {
.initialize = riscv_translate_init,
.translate_code = riscv_translate_code,
.synchronize_from_tb = riscv_cpu_synchronize_from_tb,
.restore_state_to_opc = riscv_restore_state_to_opc,

4
target/riscv/translate.c
View file

@ -1346,8 +1346,8 @@ static const TranslatorOps riscv_tr_ops = {
.tb_stop = riscv_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void riscv_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

1
target/rx/cpu.c
View file

@ -196,6 +196,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = {
static const TCGCPUOps rx_tcg_ops = {
.initialize = rx_translate_init,
.translate_code = rx_translate_code,
.synchronize_from_tb = rx_cpu_synchronize_from_tb,
.restore_state_to_opc = rx_restore_state_to_opc,
.tlb_fill = rx_cpu_tlb_fill,

2
target/rx/cpu.h
View file

@ -139,6 +139,8 @@ int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void rx_translate_init(void);
void rx_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
#include "exec/cpu-all.h"

4
target/rx/translate.c
View file

@ -2258,8 +2258,8 @@ static const TranslatorOps rx_tr_ops = {
.tb_stop = rx_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void rx_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;

1
target/s390x/cpu.c
View file

@ -362,6 +362,7 @@ void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
static const TCGCPUOps s390_tcg_ops = {
.initialize = s390x_translate_init,
.translate_code = s390x_translate_code,
.restore_state_to_opc = s390x_restore_state_to_opc,
#ifdef CONFIG_USER_ONLY

2
target/s390x/s390x-internal.h
View file

@ -399,6 +399,8 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
/* translate.c */
void s390x_translate_init(void);
void s390x_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void s390x_restore_state_to_opc(CPUState *cs,
const TranslationBlock *tb,
const uint64_t *data);

4
target/s390x/tcg/translate.c
View file

@ -6481,8 +6481,8 @@ static const TranslatorOps s390x_tr_ops = {
.disas_log = s390x_tr_disas_log,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void s390x_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc;

1
target/sh4/cpu.c
View file

@ -251,6 +251,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
static const TCGCPUOps superh_tcg_ops = {
.initialize = sh4_translate_init,
.translate_code = sh4_translate_code,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.restore_state_to_opc = superh_restore_state_to_opc,

2
target/sh4/cpu.h
View file

@ -248,6 +248,8 @@ G_NORETURN void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
uintptr_t retaddr);
void sh4_translate_init(void);
void sh4_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
#if !defined(CONFIG_USER_ONLY)
hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

4
target/sh4/translate.c
View file

@ -2318,8 +2318,8 @@ static const TranslatorOps sh4_tr_ops = {
.tb_stop = sh4_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void sh4_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;

1
target/sparc/cpu.c
View file

@ -996,6 +996,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = {
static const TCGCPUOps sparc_tcg_ops = {
.initialize = sparc_tcg_init,
.translate_code = sparc_translate_code,
.synchronize_from_tb = sparc_cpu_synchronize_from_tb,
.restore_state_to_opc = sparc_restore_state_to_opc,

2
target/sparc/cpu.h
View file

@ -609,6 +609,8 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
/* translate.c */
void sparc_tcg_init(void);
void sparc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
/* fop_helper.c */
target_ulong cpu_get_fsr(CPUSPARCState *);

4
target/sparc/translate.c
View file

@ -5819,8 +5819,8 @@ static const TranslatorOps sparc_tr_ops = {
.tb_stop = sparc_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void sparc_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc = {};

1
target/tricore/cpu.c
View file

@ -172,6 +172,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = {
static const TCGCPUOps tricore_tcg_ops = {
.initialize = tricore_tcg_init,
.translate_code = tricore_translate_code,
.synchronize_from_tb = tricore_cpu_synchronize_from_tb,
.restore_state_to_opc = tricore_restore_state_to_opc,
.tlb_fill = tricore_cpu_tlb_fill,

2
target/tricore/cpu.h
View file

@ -252,6 +252,8 @@ FIELD(TB_FLAGS, PRIV, 0, 2)
void cpu_state_reset(CPUTriCoreState *s);
void tricore_tcg_init(void);
void tricore_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)

5
target/tricore/translate.c
View file

@ -8460,9 +8460,8 @@ static const TranslatorOps tricore_tr_ops = {
.tb_stop = tricore_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void tricore_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc,

1
target/xtensa/cpu.c
View file

@ -232,6 +232,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
static const TCGCPUOps xtensa_tcg_ops = {
.initialize = xtensa_translate_init,
.translate_code = xtensa_translate_code,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,

2
target/xtensa/cpu.h
View file

@ -617,6 +617,8 @@ G_NORETURN void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
void xtensa_collect_sr_names(const XtensaConfig *config);
void xtensa_translate_init(void);
void xtensa_translate_code(CPUState *cs, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc);
void **xtensa_get_regfile_by_name(const char *name, int entries, int bits);
void xtensa_breakpoint_handler(CPUState *cs);
void xtensa_register_core(XtensaConfigList *node);

4
target/xtensa/translate.c
View file

@ -1228,8 +1228,8 @@ static const TranslatorOps xtensa_translator_ops = {
.tb_stop = xtensa_tr_tb_stop,
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
vaddr pc, void *host_pc)
void xtensa_translate_code(CPUState *cpu, TranslationBlock *tb,
int *max_insns, vaddr pc, void *host_pc)
{
DisasContext dc = {};
translator_loop(cpu, tb, max_insns, pc, host_pc,