Jason Chien e5d28bf2b3 hw/riscv/riscv-iommu.c: Correct the validness check of iova ... From RISCV IOMMU spec section 2.1.3: When SXL is 1, the following rules apply: - If the first-stage is not Bare, then a page fault corresponding to the original access type occurs if the IOVA has bits beyond bit 31 set to 1. - If the second-stage is not Bare, then a guest page fault corresponding to the original access type occurs if the incoming GPA has bits beyond bit 33 set to 1. From RISCV IOMMU spec section 2.3 step 17: Use the process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification to determine the GPA accessed by the transaction. From RISCV IOMMU spec section 2.3 step 19: Use the second-stage address translation process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification to translate the GPA A to determine the SPA accessed by the transaction. This commit adds the iova check with the following rules: - For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero extended. - For Sv39, Sv48 and Sv57, the iova must be signed extended with most significant bit. Signed-off-by: Jason Chien <jason.chien@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241114065617.25133-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-12-20 11:19:16 +10:00
..
boot.c	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
Kconfig	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
meson.build	hw/riscv: add riscv-iommu-pci reference device	2024-10-31 13:51:24 +10:00
microchip_pfsoc.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
riscv-iommu-bits.h	hw/riscv/riscv-iommu: add DBG support	2024-10-31 13:51:24 +10:00
riscv-iommu-pci.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
riscv-iommu.c	hw/riscv/riscv-iommu.c: Correct the validness check of iova	2024-12-20 11:19:16 +10:00
riscv-iommu.h	hw/riscv/riscv-iommu: add ATS support	2024-10-31 13:51:24 +10:00
riscv_hart.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
shakti_c.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
sifive_e.c	hw: Remove unused inclusion of hw/char/serial.h	2024-10-03 19:33:23 +02:00
sifive_u.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
spike.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
trace-events	hw/riscv/riscv-iommu: add ATS support	2024-10-31 13:51:24 +10:00
trace.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
virt-acpi-build.c	hw/riscv/virt-acpi-build.c: Update the HID of RISC-V UART	2024-07-22 20:15:42 -04:00
virt.c	hw/riscv/virt: Remove pointless GPEX_HOST() cast	2024-12-13 15:27:08 +01:00