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hw/riscv: Constify all Property

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Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-13 16:43:40 +00:00
parent 4ef4c30d2e
commit 766bade2da
5 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
hw/riscv/opentitan.c
View file

@ -306,7 +306,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
}
static Property lowrisc_ibex_soc_props[] = {
static const Property lowrisc_ibex_soc_props[] = {
DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
DEFINE_PROP_END_OF_LIST()
};

2
hw/riscv/riscv-iommu-pci.c
View file

@ -157,7 +157,7 @@ static void riscv_iommu_pci_init(Object *obj)
iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;
}
static Property riscv_iommu_pci_properties[] = {
static const Property riscv_iommu_pci_properties[] = {
DEFINE_PROP_UINT16("vendor-id", RISCVIOMMUStatePci, vendor_id,
PCI_VENDOR_ID_REDHAT),
DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id,

2
hw/riscv/riscv-iommu.c
View file

@ -2235,7 +2235,7 @@ static void riscv_iommu_unrealize(DeviceState *dev)
g_hash_table_unref(s->ctx_cache);
}
static Property riscv_iommu_properties[] = {
static const Property riscv_iommu_properties[] = {
DEFINE_PROP_UINT32("version", RISCVIOMMUState, version,
RISCV_IOMMU_SPEC_DOT_VER),
DEFINE_PROP_UINT32("bus", RISCVIOMMUState, bus, 0x0),

2
hw/riscv/riscv_hart.c
View file

@ -27,7 +27,7 @@
#include "hw/qdev-properties.h"
#include "hw/riscv/riscv_hart.h"
static Property riscv_harts_props[] = {
static const Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),

2
hw/riscv/sifive_u.c
View file

@ -936,7 +936,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
}
static Property sifive_u_soc_props[] = {
static const Property sifive_u_soc_props[] = {
DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
DEFINE_PROP_END_OF_LIST()