Jim Shu b4132a9e62 hw/riscv: Support to load DTB after 3GB memory on 64-bit system. ... Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241120153935.24706-2-jim.shu@sifive.com> [ Changes by AF - Store fdt_load_addr_hi32 in the reset vector ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-12-20 11:22:47 +10:00
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boot.c	hw/riscv: Support to load DTB after 3GB memory on 64-bit system.	2024-12-20 11:22:47 +10:00
Kconfig	hw/riscv: Add Microblaze V generic board	2024-12-20 11:22:47 +10:00
meson.build	hw/riscv: Add Microblaze V generic board	2024-12-20 11:22:47 +10:00
microblaze-v-generic.c	hw/riscv: Add Microblaze V generic board	2024-12-20 11:22:47 +10:00
microchip_pfsoc.c	hw/riscv: Support to load DTB after 3GB memory on 64-bit system.	2024-12-20 11:22:47 +10:00
numa.c	hw/riscv/numa.c: use g_autofree in socket_fdt_write_distance_matrix()	2024-02-09 20:43:14 +10:00
opentitan.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
riscv-iommu-bits.h	hw/riscv/riscv-iommu: parametrize CAP.IGS	2024-12-20 11:19:16 +10:00
riscv-iommu-pci.c	hw/riscv/riscv-iommu: implement reset protocol	2024-12-20 11:22:46 +10:00
riscv-iommu-sys.c	hw/riscv/riscv-iommu: implement reset protocol	2024-12-20 11:22:46 +10:00
riscv-iommu.c	hw/riscv/riscv-iommu: implement reset protocol	2024-12-20 11:22:46 +10:00
riscv-iommu.h	hw/riscv/riscv-iommu: implement reset protocol	2024-12-20 11:22:46 +10:00
riscv_hart.c	hw/riscv: Constify all Property	2024-12-15 12:56:03 -06:00
shakti_c.c	hw/riscv: Respect firmware ELF entry point	2024-10-02 15:11:51 +10:00
sifive_e.c	hw: Remove unused inclusion of hw/char/serial.h	2024-10-03 19:33:23 +02:00
sifive_u.c	hw/riscv: Support to load DTB after 3GB memory on 64-bit system.	2024-12-20 11:22:47 +10:00
spike.c	hw/riscv: Support to load DTB after 3GB memory on 64-bit system.	2024-12-20 11:22:47 +10:00
trace-events	hw/riscv/riscv-iommu: implement reset protocol	2024-12-20 11:22:46 +10:00
trace.h	hw/riscv: add RISC-V IOMMU base emulation	2024-10-31 13:51:24 +10:00
virt-acpi-build.c	hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format	2024-12-20 11:22:47 +10:00
virt.c	hw/riscv: Support to load DTB after 3GB memory on 64-bit system.	2024-12-20 11:22:47 +10:00