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https://github.com/Motorhead1991/qemu.git
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a9983f8129
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
107 lines
3.8 KiB
C
107 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific opcode support
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* Copyright (c) 2018 SiFive, Inc
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*/
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#ifndef TCG_TARGET_HAS_H
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#define TCG_TARGET_HAS_H
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#include "host/cpuinfo.h"
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/* optional instructions */
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#define TCG_TARGET_HAS_negsetcond_i32 1
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_div2_i32 0
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#define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#define TCG_TARGET_HAS_negsetcond_i64 1
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_div2_i64 0
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#define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB)
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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#define TCG_TARGET_HAS_mulu2_i64 0
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#define TCG_TARGET_HAS_muls2_i64 0
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_tst 0
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/* vector instructions */
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#define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X)
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#define TCG_TARGET_HAS_andc_vec 0
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#define TCG_TARGET_HAS_orc_vec 0
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#define TCG_TARGET_HAS_nand_vec 0
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#define TCG_TARGET_HAS_nor_vec 0
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#define TCG_TARGET_HAS_eqv_vec 0
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#define TCG_TARGET_HAS_not_vec 1
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#define TCG_TARGET_HAS_neg_vec 1
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#define TCG_TARGET_HAS_abs_vec 0
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#define TCG_TARGET_HAS_roti_vec 1
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#define TCG_TARGET_HAS_rots_vec 1
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#define TCG_TARGET_HAS_rotv_vec 1
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec 1
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 0
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#define TCG_TARGET_HAS_cmpsel_vec 1
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#define TCG_TARGET_HAS_tst_vec 0
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static inline bool
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tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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/* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
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return ofs || (cpuinfo & CPUINFO_ZBA);
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}
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switch (len) {
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case 1:
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return (cpuinfo & CPUINFO_ZBS) && ofs != 0;
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case 16:
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return (cpuinfo & CPUINFO_ZBB) && ofs == 0;
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}
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return false;
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}
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#define TCG_TARGET_extract_valid tcg_target_extract_valid
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static inline bool
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tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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return true;
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}
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return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
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}
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#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
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#define TCG_TARGET_deposit_valid(type, ofs, len) 0
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#endif
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