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tcg: Convert mulsh to TCGOutOpBinary

Browse source 
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-07 11:13:05 -08:00
parent aa28c9ef8e
commit a9983f8129
23 changed files with 95 additions and 72 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tcg/aarch64/tcg-target-has.h
View file

@ -27,7 +27,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -46,7 +45,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 1
/*
* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,

17
tcg/aarch64/tcg-target.c.inc
View file

@ -2184,6 +2184,18 @@ static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)
return type == TCG_TYPE_I64 ? C_O1_I2(r, r, r) : C_NotImplemented;
}
static void tgen_mulsh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
}
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_mulh,
.out_rrr = tgen_mulsh,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -2543,10 +2555,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
args[5], const_args[4], const_args[5], true);
break;
case INDEX_op_mulsh_i64:
tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
@ -3057,7 +3065,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_rem_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
case INDEX_op_mulsh_i64:
return C_O1_I2(r, r, r);
case INDEX_op_shl_i32:

1
tcg/arm/tcg-target-has.h
View file

@ -34,7 +34,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
#define TCG_TARGET_HAS_rem_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0

4
tcg/arm/tcg-target.c.inc
View file

@ -1890,6 +1890,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/i386/tcg-target-has.h
View file

@ -39,7 +39,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_mulsh_i32 0
#if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */
@ -58,7 +57,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#else
#define TCG_TARGET_HAS_qemu_st8_i32 1

4
tcg/i386/tcg-target.c.inc
View file

@ -2664,6 +2664,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/loongarch64/tcg-target-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_clz_i32 1
@ -46,7 +45,6 @@
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX)

24
tcg/loongarch64/tcg-target.c.inc
View file

@ -1347,6 +1347,21 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static void tgen_mulsh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type == TCG_TYPE_I32) {
tcg_out_opc_mulh_w(s, a0, a1, a2);
} else {
tcg_out_opc_mulh_d(s, a0, a1, a2);
}
}
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_mulsh,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -1656,13 +1671,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_mulsh_i32:
tcg_out_opc_mulh_w(s, a0, a1, a2);
break;
case INDEX_op_mulsh_i64:
tcg_out_opc_mulh_d(s, a0, a1, a2);
break;
case INDEX_op_div_i32:
tcg_out_opc_div_w(s, a0, a1, a2);
break;
@ -2349,8 +2357,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_setcond_i64:
return C_O1_I2(r, rz, rJ);
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_divu_i32:

2
tcg/mips/tcg-target-has.h
View file

@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 0
@ -58,7 +57,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
#define TCG_TARGET_HAS_negsetcond_i64 0

34
tcg/mips/tcg-target.c.inc
View file

@ -1743,6 +1743,24 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static void tgen_mulsh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (use_mips32r6_instructions) {
MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH;
tcg_out_opc_reg(s, insn, a0, a1, a2);
} else {
MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT;
tcg_out_opc_reg(s, insn, 0, a1, a2);
tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0);
}
}
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_mulsh,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -1921,13 +1939,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_ldst(s, i1, a0, a1, a2);
break;
case INDEX_op_mulsh_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
break;
}
i1 = OPC_MULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i32:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
@ -1956,13 +1967,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
i1 = OPC_DIVU, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_mulsh_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
break;
}
i1 = OPC_DMULT, i2 = OPC_MFHI;
goto do_hilo1;
case INDEX_op_div_i64:
if (use_mips32r6_instructions) {
tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
@ -2249,13 +2253,11 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64:
return C_O0_I2(rz, r);
case INDEX_op_mulsh_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_setcond_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:

2
tcg/ppc/tcg-target-has.h
View file

@ -29,7 +29,6 @@
#define TCG_TARGET_HAS_negsetcond_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
@ -51,7 +50,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 1
#endif
#define TCG_TARGET_HAS_qemu_ldst_i128 \

21
tcg/ppc/tcg-target.c.inc
View file

@ -2984,6 +2984,18 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static void tgen_mulsh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
uint32_t insn = type == TCG_TYPE_I32 ? MULHW : MULHD;
tcg_out32(s, insn | TAB(a0, a1, a2));
}
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_mulsh,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -3499,13 +3511,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_mulsh_i32:
tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mulsh_i64:
tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
break;
case INDEX_op_mb:
tcg_out_mb(s, args[0]);
break;
@ -4183,12 +4188,10 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
case INDEX_op_mulsh_i64:
return C_O1_I2(r, r, r);
case INDEX_op_clz_i32:

2
tcg/riscv/tcg-target-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB)
@ -45,7 +44,6 @@
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_qemu_ldst_i128 0

19
tcg/riscv/tcg-target.c.inc
View file

@ -2026,6 +2026,18 @@ static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)
return type == TCG_TYPE_I32 ? C_NotImplemented : C_O1_I2(r, r, r);
}
static void tgen_mulsh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
}
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_mulh,
.out_rrr = tgen_mulsh,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
@ -2391,11 +2403,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32);
break;
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2);
break;
case INDEX_op_mb:
tcg_out_mb(s, a0);
break;
@ -2723,12 +2730,10 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_negsetcond_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_mulsh_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_rem_i32:
case INDEX_op_remu_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_div_i64:
case INDEX_op_divu_i64:
case INDEX_op_rem_i64:

2
tcg/s390x/tcg-target-has.h
View file

@ -42,7 +42,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
@ -60,7 +59,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2)
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 1

4
tcg/s390x/tcg-target.c.inc
View file

@ -2309,6 +2309,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};

2
tcg/sparc64/tcg-target-has.h
View file

@ -28,7 +28,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
@ -47,7 +46,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0

4
tcg/sparc64/tcg-target.c.inc
View file

@ -1357,6 +1357,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rri = tgen_muli,
};
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_NotImplemented,
};
static void tgen_muluh(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{

1
tcg/tcg-has.h
View file

@ -28,7 +28,6 @@
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_mulsh_i64 0
/* Turn some undef macros into true macros. */
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1

4
tcg/tcg-op.c
View file

@ -1156,7 +1156,7 @@ void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_muls2_i32) {
tcg_gen_op4_i32(INDEX_op_muls2_i32, rl, rh, arg1, arg2);
} else if (TCG_TARGET_HAS_mulsh_i32) {
} else if (tcg_op_supported(INDEX_op_mulsh_i32, TCG_TYPE_I32, 0)) {
TCGv_i32 t = tcg_temp_ebb_new_i32();
tcg_gen_op3_i32(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i32(INDEX_op_mulsh_i32, rh, arg1, arg2);
@ -2861,7 +2861,7 @@ void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (TCG_TARGET_HAS_muls2_i64) {
tcg_gen_op4_i64(INDEX_op_muls2_i64, rl, rh, arg1, arg2);
} else if (TCG_TARGET_HAS_mulsh_i64) {
} else if (tcg_op_supported(INDEX_op_mulsh_i64, TCG_TYPE_I64, 0)) {
TCGv_i64 t = tcg_temp_ebb_new_i64();
tcg_gen_op3_i64(INDEX_op_mul, t, arg1, arg2);
tcg_gen_op3_i64(INDEX_op_mulsh_i64, rh, arg1, arg2);

8
tcg/tcg.c
View file

@ -1022,6 +1022,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_eqv, TCGOutOpBinary, outop_eqv),
OUTOP(INDEX_op_mul, TCGOutOpBinary, outop_mul),
OUTOP(INDEX_op_mulsh_i32, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_mulsh_i64, TCGOutOpBinary, outop_mulsh),
OUTOP(INDEX_op_muluh, TCGOutOpBinary, outop_muluh),
OUTOP(INDEX_op_nand, TCGOutOpBinary, outop_nand),
OUTOP(INDEX_op_neg, TCGOutOpUnary, outop_neg),
@ -2281,8 +2283,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_mulu2_i32;
case INDEX_op_muls2_i32:
return TCG_TARGET_HAS_muls2_i32;
case INDEX_op_mulsh_i32:
return TCG_TARGET_HAS_mulsh_i32;
case INDEX_op_bswap16_i32:
return TCG_TARGET_HAS_bswap16_i32;
case INDEX_op_bswap32_i32:
@ -2361,8 +2361,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_mulu2_i64;
case INDEX_op_muls2_i64:
return TCG_TARGET_HAS_muls2_i64;
case INDEX_op_mulsh_i64:
return TCG_TARGET_HAS_mulsh_i64;
case INDEX_op_mov_vec:
case INDEX_op_dup_vec:
@ -5426,6 +5424,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_andc:
case INDEX_op_eqv:
case INDEX_op_mul:
case INDEX_op_mulsh_i32:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh:
case INDEX_op_nand:
case INDEX_op_nor:

2
tcg/tci/tcg-target-has.h
View file

@ -18,7 +18,6 @@
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_negsetcond_i32 0
#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_mulsh_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
@ -41,7 +40,6 @@
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_mulsh_i64 0
#else
#define TCG_TARGET_HAS_mulu2_i32 1
#endif /* TCG_TARGET_REG_BITS == 64 */

4
tcg/tci/tcg-target.c.inc
View file

@ -670,6 +670,10 @@ static const TCGOutOpBinary outop_mul = {
.out_rrr = tgen_mul,
};
static const TCGOutOpBinary outop_mulsh = {
.base.static_constraint = C_NotImplemented,
};
static const TCGOutOpBinary outop_muluh = {
.base.static_constraint = C_NotImplemented,
};