mirror of
https://github.com/Motorhead1991/qemu.git
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a341c84e81
At the same time, drop all backend support for immediate operands, as we now transform andc to and during optimize. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific opcode support
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* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
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* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
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*/
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#ifndef TCG_TARGET_HAS_H
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#define TCG_TARGET_HAS_H
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/* MOVN/MOVZ instructions detection */
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#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
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defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
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defined(_MIPS_ARCH_MIPS4)
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#define use_movnz_instructions 1
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#else
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extern bool use_movnz_instructions;
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#endif
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/* MIPS32 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
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#define use_mips32_instructions 1
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#else
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extern bool use_mips32_instructions;
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#endif
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/* MIPS32R2 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
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#define use_mips32r2_instructions 1
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#else
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extern bool use_mips32r2_instructions;
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#endif
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/* MIPS32R6 instruction set detection */
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#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
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#define use_mips32r6_instructions 1
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#else
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#define use_mips32r6_instructions 0
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#endif
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/* optional instructions */
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#define TCG_TARGET_HAS_div_i32 1
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#define TCG_TARGET_HAS_rem_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muluh_i32 1
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#define TCG_TARGET_HAS_mulsh_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_negsetcond_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#define TCG_TARGET_HAS_div_i64 1
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#define TCG_TARGET_HAS_rem_i64 1
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#define TCG_TARGET_HAS_not_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_orc_i64 0
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#define TCG_TARGET_HAS_eqv_i64 0
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#define TCG_TARGET_HAS_nand_i64 0
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#define TCG_TARGET_HAS_add2_i64 0
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#define TCG_TARGET_HAS_sub2_i64 0
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#define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
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#define TCG_TARGET_HAS_muluh_i64 1
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_ext32s_i64 1
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#define TCG_TARGET_HAS_ext32u_i64 1
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#define TCG_TARGET_HAS_negsetcond_i64 0
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#endif
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/* optional instructions detected at runtime */
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ctz_i32 0
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_qemu_st8_i32 0
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_bswap16_i64 1
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#define TCG_TARGET_HAS_bswap32_i64 1
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#define TCG_TARGET_HAS_bswap64_i64 1
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions
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#define TCG_TARGET_HAS_ctz_i64 0
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#define TCG_TARGET_HAS_ctpop_i64 0
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#endif
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#define TCG_TARGET_HAS_qemu_ldst_i128 0
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#define TCG_TARGET_HAS_tst 0
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#define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions
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#define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions
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static inline bool
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tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (ofs == 0) {
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switch (len) {
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case 8:
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case 16:
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return use_mips32r2_instructions;
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case 32:
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return type == TCG_TYPE_I64;
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}
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}
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return false;
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}
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#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
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#endif
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