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tcg: Convert andc to TCGOutOpBinary

Browse source 
At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-06 12:26:28 -08:00
parent 93a9ddb84a
commit a341c84e81
28 changed files with 135 additions and 130 deletions
Download patch file Download diff file Expand all files Collapse all files

2
tcg/aarch64/tcg-target-has.h
View file

@ -19,7 +19,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
@ -45,7 +44,6 @@
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0

24
tcg/aarch64/tcg-target.c.inc
View file

@ -2146,6 +2146,17 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_insn(s, 3510, BIC, type, a0, a1, a2);
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2227,17 +2238,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext,
tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
break;
case INDEX_op_andc_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
case INDEX_op_andc_i64:
if (c2) {
tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
} else {
tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
}
break;
case INDEX_op_or_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@ -3020,8 +3020,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:

1
tcg/arm/tcg-target-has.h
View file

@ -28,7 +28,6 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0

16
tcg/arm/tcg-target.c.inc
View file

@ -1870,6 +1870,17 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_BIC, a0, a1, a2, SHIFT_IMM_LSL(0));
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1932,10 +1943,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
args[0], args[1], args[2], const_args[2]);
}
break;
case INDEX_op_andc_i32:
tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND,
args[0], args[1], args[2], const_args[2]);
break;
case INDEX_op_or_i32:
c = ARITH_ORR;
goto gen_arith;
@ -2189,7 +2196,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_negsetcond_i32:
return C_O1_I2(r, r, rIN);
case INDEX_op_andc_i32:
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
return C_O1_I2(r, r, rIK);

2
tcg/i386/tcg-target-con-set.h
View file

@ -42,9 +42,9 @@ C_O1_I2(r, 0, reZ)
C_O1_I2(r, 0, ri)
C_O1_I2(r, 0, rI)
C_O1_I2(r, L, L)
C_O1_I2(r, r, r)
C_O1_I2(r, r, re)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(x, x, x)
C_N1_I2(r, r, r)
C_N1_I2(r, r, rW)

2
tcg/i386/tcg-target-has.h
View file

@ -31,7 +31,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_andc_i32 have_bmi1
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@ -57,7 +56,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_andc_i64 have_bmi1
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0

31
tcg/i386/tcg-target.c.inc
View file

@ -2615,6 +2615,24 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
int rexw = type == TCG_TYPE_I32 ? 0 : P_REXW;
tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
}
static TCGConstraintSetIndex cset_andc(TCGType type, unsigned flags)
{
return have_bmi1 ? C_O1_I2(r, r, r) : C_NotImplemented;
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_andc,
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2713,15 +2731,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
OP_32_64(andc):
if (const_a2) {
tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1);
tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0);
} else {
tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1);
}
break;
OP_32_64(mul):
if (const_a2) {
int32_t val;
@ -3642,10 +3651,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_xor_i64:
return C_O1_I2(r, 0, re);
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
case INDEX_op_shr_i32:

1
tcg/loongarch64/tcg-target-con-set.h
View file

@ -22,6 +22,7 @@ C_O0_I3(r, r, r)
C_O1_I1(r, r)
C_O1_I1(w, r)
C_O1_I1(w, w)
C_O1_I2(r, r, r)
C_O1_I2(r, r, rC)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)

2
tcg/loongarch64/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@ -47,7 +46,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0

23
tcg/loongarch64/tcg-target.c.inc
View file

@ -1321,6 +1321,17 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_andn(s, a0, a1, a2);
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1371,16 +1382,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
if (c2) {
/* guaranteed to fit due to constraint */
tcg_out_opc_andi(s, a0, a1, ~a2);
} else {
tcg_out_opc_andn(s, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
@ -2276,8 +2277,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_qemu_ld_i64:
return C_O1_I1(r, r);
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
/*

2
tcg/mips/tcg-target-has.h
View file

@ -43,7 +43,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_andc_i32 0
#define TCG_TARGET_HAS_orc_i32 0
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@ -63,7 +62,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_andc_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0

4
tcg/mips/tcg-target.c.inc
View file

@ -1708,6 +1708,10 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_NotImplemented,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],

2
tcg/ppc/tcg-target-has.h
View file

@ -23,7 +23,6 @@
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@ -50,7 +49,6 @@
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1

29
tcg/ppc/tcg-target.c.inc
View file

@ -2943,6 +2943,17 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out32(s, ANDC | SAB(a1, a0, a2));
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -3046,22 +3057,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out32(s, XOR | SAB(a1, a0, a2));
}
break;
case INDEX_op_andc_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi32(s, a0, a1, ~a2);
} else {
tcg_out32(s, ANDC | SAB(a1, a0, a2));
}
break;
case INDEX_op_andc_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_andi64(s, a0, a1, ~a2);
} else {
tcg_out32(s, ANDC | SAB(a1, a0, a2));
}
break;
case INDEX_op_orc_i32:
if (const_args[2]) {
tcg_out_ori32(s, args[0], args[1], ~args[2]);
@ -4137,7 +4132,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
case INDEX_op_andc_i32:
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32:
case INDEX_op_shl_i32:
@ -4145,7 +4139,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sar_i32:
case INDEX_op_rotl_i32:
case INDEX_op_rotr_i32:
case INDEX_op_andc_i64:
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:

1
tcg/riscv/tcg-target-con-set.h
View file

@ -13,6 +13,7 @@ C_O0_I1(r)
C_O0_I2(rz, r)
C_O0_I2(rz, rz)
C_O1_I1(r, r)
C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)

2
tcg/riscv/tcg-target-has.h
View file

@ -25,7 +25,6 @@
#define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i32 0
@ -46,7 +45,6 @@
#define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB)
#define TCG_TARGET_HAS_nand_i64 0

27
tcg/riscv/tcg-target.c.inc
View file

@ -1996,6 +1996,23 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
}
static TCGConstraintSetIndex cset_zbb_rrr(TCGType type, unsigned flags)
{
return cpuinfo & CPUINFO_ZBB ? C_O1_I2(r, r, r) : C_NotImplemented;
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_zbb_rrr,
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -2092,14 +2109,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
if (c2) {
tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2);
} else {
tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
if (c2) {
@ -2683,8 +2692,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_negsetcond_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_orc_i32:
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:

1
tcg/s390x/tcg-target-con-set.h
View file

@ -31,7 +31,6 @@ C_O1_I2(r, r, rC)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, r, rK)
C_O1_I2(r, r, rKR)
C_O1_I2(r, r, rNK)
C_O1_I2(r, r, rNKR)
C_O1_I2(r, rZ, r)

2
tcg/s390x/tcg-target-has.h
View file

@ -34,7 +34,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_not_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_andc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i32 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i32 HAVE_FACILITY(MISC_INSN_EXT3)
@ -59,7 +58,6 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
#define TCG_TARGET_HAS_not_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_andc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_orc_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_eqv_i64 HAVE_FACILITY(MISC_INSN_EXT3)
#define TCG_TARGET_HAS_nand_i64 HAVE_FACILITY(MISC_INSN_EXT3)

42
tcg/s390x/tcg-target.c.inc
View file

@ -2221,6 +2221,27 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi_3,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
if (type == TCG_TYPE_I32) {
tcg_out_insn(s, RRFa, NCRK, a0, a1, a2);
} else {
tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2);
}
}
static TCGConstraintSetIndex cset_misc3_rrr(TCGType type, unsigned flags)
{
return HAVE_FACILITY(MISC_INSN_EXT3) ? C_O1_I2(r, r, r) : C_NotImplemented;
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_Dynamic,
.base.dynamic_constraint = cset_misc3_rrr,
.out_rrr = tgen_andc,
};
# define OP_32_64(x) \
case glue(glue(INDEX_op_,x),_i32): \
@ -2312,15 +2333,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_andc_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I32, a0, a1);
tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2);
} else {
tcg_out_insn(s, RRFa, NCRK, a0, a1, a2);
}
break;
case INDEX_op_orc_i32:
a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];
if (const_args[2]) {
@ -2568,15 +2580,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
}
break;
case INDEX_op_andc_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
tcg_out_mov(s, TCG_TYPE_I64, a0, a1);
tgen_andi(s, TCG_TYPE_I64, a0, ~a2);
} else {
tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2);
}
break;
case INDEX_op_orc_i64:
a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
@ -3286,12 +3289,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_xor_i64:
return C_O1_I2(r, r, rK);
case INDEX_op_andc_i32:
case INDEX_op_orc_i32:
case INDEX_op_eqv_i32:
return C_O1_I2(r, r, ri);
case INDEX_op_andc_i64:
return C_O1_I2(r, r, rKR);
case INDEX_op_orc_i64:
case INDEX_op_eqv_i64:
return C_O1_I2(r, r, rNK);

2
tcg/sparc64/tcg-target-has.h
View file

@ -20,7 +20,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap16_i32 0
#define TCG_TARGET_HAS_bswap32_i32 0
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_eqv_i32 0
#define TCG_TARGET_HAS_nand_i32 0
@ -46,7 +45,6 @@ extern bool use_vis3_instructions;
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0

16
tcg/sparc64/tcg-target.c.inc
View file

@ -1322,6 +1322,17 @@ static const TCGOutOpBinary outop_and = {
.out_rri = tgen_andi,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_arith(s, a0, a1, a2, ARITH_ANDN);
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -1379,9 +1390,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
OP_32_64(sub):
c = ARITH_SUB;
goto gen_arith;
OP_32_64(andc):
c = ARITH_ANDN;
goto gen_arith;
OP_32_64(or):
c = ARITH_OR;
goto gen_arith;
@ -1604,8 +1612,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_divu_i64:
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_or_i32:
case INDEX_op_or_i64:
case INDEX_op_orc_i32:

1
tcg/tcg-has.h
View file

@ -20,7 +20,6 @@
#define TCG_TARGET_HAS_bswap32_i64 0
#define TCG_TARGET_HAS_bswap64_i64 0
#define TCG_TARGET_HAS_not_i64 0
#define TCG_TARGET_HAS_andc_i64 0
#define TCG_TARGET_HAS_orc_i64 0
#define TCG_TARGET_HAS_eqv_i64 0
#define TCG_TARGET_HAS_nand_i64 0

4
tcg/tcg-op.c
View file

@ -668,7 +668,7 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (TCG_TARGET_HAS_andc_i32) {
if (tcg_op_supported(INDEX_op_andc_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_andc_i32, ret, arg1, arg2);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@ -2264,7 +2264,7 @@ void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
} else if (TCG_TARGET_HAS_andc_i64) {
} else if (tcg_op_supported(INDEX_op_andc_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_andc_i64, ret, arg1, arg2);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();

8
tcg/tcg.c
View file

@ -1006,6 +1006,8 @@ QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) -
static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_add, TCGOutOpBinary, outop_add),
OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and),
OUTOP(INDEX_op_andc_i32, TCGOutOpBinary, outop_andc),
OUTOP(INDEX_op_andc_i64, TCGOutOpBinary, outop_andc),
};
#undef OUTOP
@ -2269,8 +2271,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap32_i32;
case INDEX_op_not_i32:
return TCG_TARGET_HAS_not_i32;
case INDEX_op_andc_i32:
return TCG_TARGET_HAS_andc_i32;
case INDEX_op_orc_i32:
return TCG_TARGET_HAS_orc_i32;
case INDEX_op_eqv_i32:
@ -2346,8 +2346,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
return TCG_TARGET_HAS_bswap64_i64;
case INDEX_op_not_i64:
return TCG_TARGET_HAS_not_i64;
case INDEX_op_andc_i64:
return TCG_TARGET_HAS_andc_i64;
case INDEX_op_orc_i64:
return TCG_TARGET_HAS_orc_i64;
case INDEX_op_eqv_i64:
@ -5443,6 +5441,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_add:
case INDEX_op_and:
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
{
const TCGOutOpBinary *out =
container_of(all_outop[op->opc], TCGOutOpBinary, base);

2
tcg/tci.c
View file

@ -547,12 +547,10 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
CASE_32_64(andc)
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] & ~regs[r2];
break;
#endif
#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
CASE_32_64(orc)
tci_args_rrr(insn, &r0, &r1, &r2);

2
tcg/tci/tcg-target-has.h
View file

@ -11,7 +11,6 @@
#define TCG_TARGET_HAS_bswap32_i32 1
#define TCG_TARGET_HAS_div_i32 1
#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_extract2_i32 0
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 1
@ -36,7 +35,6 @@
#define TCG_TARGET_HAS_extract2_i64 0
#define TCG_TARGET_HAS_div_i64 1
#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_andc_i64 1
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 1
#define TCG_TARGET_HAS_nor_i64 1

14
tcg/tci/tcg-target.c.inc
View file

@ -95,8 +95,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
case INDEX_op_nand_i32:
@ -659,6 +657,17 @@ static const TCGOutOpBinary outop_and = {
.out_rrr = tgen_and,
};
static void tgen_andc(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_op_rrr(s, glue(INDEX_op_andc_i,TCG_TARGET_REG_BITS), a0, a1, a2);
}
static const TCGOutOpBinary outop_andc = {
.base.static_constraint = C_O1_I2(r, r, r),
.out_rrr = tgen_andc,
};
static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
@ -705,7 +714,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
CASE_32_64(mul)
CASE_32_64(or)
CASE_32_64(xor)
CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */
CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */
CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */
CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */