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Vendor CPUs that set RVG are displaying user warnings about other extensions that RVG must enable, one warning per CPU. E.g.: $ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei This happens because we decided a while ago that, for simplicity, vendor CPUs could set RVG instead of setting each G extension individually in their cpu_init(). Our warning isn't taking that into account, and we're bugging users with a warning that we're causing ourselves. In a closer look we conclude that this warning is not warranted in any other circumstance since we're just following the ISA [1], which states in chapter 24: "One goal of the RISC-V project is that it be used as a stable software development target. For this purpose, we define a combination of a base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for the IMAFDZicsr Zifencei combination of instruction-set extensions." With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly enables 'G' is an expected behavior and the warning is unneeded. Any user caught by surprise should refer to the ISA. Remove the warning when handling RVG. [1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf Reported-by: Paul A. Clarke <pclarke@ventanamicro.com> Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| .. | ||
| insn_trans | ||
| kvm | ||
| tcg | ||
| arch_dump.c | ||
| bitmanip_helper.c | ||
| common-semi-target.h | ||
| cpu-param.h | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| cpu_bits.h | ||
| cpu_cfg.h | ||
| cpu_helper.c | ||
| cpu_user.h | ||
| cpu_vendorid.h | ||
| crypto_helper.c | ||
| csr.c | ||
| debug.c | ||
| debug.h | ||
| fpu_helper.c | ||
| gdbstub.c | ||
| helper.h | ||
| insn16.decode | ||
| insn32.decode | ||
| instmap.h | ||
| internals.h | ||
| Kconfig | ||
| m128_helper.c | ||
| machine.c | ||
| meson.build | ||
| monitor.c | ||
| op_helper.c | ||
| pmp.c | ||
| pmp.h | ||
| pmu.c | ||
| pmu.h | ||
| riscv-qmp-cmds.c | ||
| sbi_ecall_interface.h | ||
| time_helper.c | ||
| time_helper.h | ||
| trace-events | ||
| trace.h | ||
| translate.c | ||
| vcrypto_helper.c | ||
| vector_helper.c | ||
| vector_internals.c | ||
| vector_internals.h | ||
| xthead.decode | ||
| XVentanaCondOps.decode | ||
| zce_helper.c | ||