qemu/target
Daniel Henrique Barboza 9b9741c38f target/riscv/tcg: remove RVG warning
Vendor CPUs that set RVG are displaying user warnings about other
extensions that RVG must enable, one warning per CPU. E.g.:

$ ./build/qemu-system-riscv64 -smp 8 -M virt -cpu veyron-v1 -nographic
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei
qemu-system-riscv64: warning: Setting G will also set IMAFD_Zicsr_Zifencei

This happens because we decided a while ago that, for simplicity, vendor
CPUs could set RVG instead of setting each G extension individually in
their cpu_init(). Our warning isn't taking that into account, and we're
bugging users with a warning that we're causing ourselves.

In a closer look we conclude that this warning is not warranted in any
other circumstance since we're just following the ISA [1], which states
in chapter 24:

"One goal of the RISC-V project is that it be used as a stable software
development target. For this purpose, we define a combination of a base
ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr,
Zifencei) as a 'general-purpose' ISA, and we use the abbreviation G for
the IMAFDZicsr Zifencei combination of instruction-set extensions."

With this in mind, enabling IMAFD_Zicsr_Zifencei if the user explicitly
enables 'G' is an expected behavior and the warning is unneeded. Any
user caught by surprise should refer to the ISA.

Remove the warning when handling RVG.

[1] https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf

Reported-by: Paul A. Clarke <pclarke@ventanamicro.com>
Suggested-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20231003122539.775932-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12 12:39:45 +10:00
..
alpha meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
arm target/arm: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
avr meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
cris meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
hexagon accel/tcg: Remove cpu_set_cpustate_pointers 2023-10-04 11:03:54 -07:00
hppa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
i386 hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
loongarch hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
m68k meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
microblaze meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
mips meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
nios2 meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
openrisc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
ppc target/ppc: Remove references to gdb_has_xml 2023-10-11 08:46:33 +01:00
riscv target/riscv/tcg: remove RVG warning 2023-10-12 12:39:45 +10:00
rx meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
s390x hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
sh4 target/sh4: Disable decode_gusa when plugins enabled 2023-10-11 08:46:36 +01:00
sparc meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
tricore hw/core/cpu: Return static value with gdb_arch_name() 2023-10-11 08:46:33 +01:00
xtensa meson: Rename target_softmmu_arch -> target_system_arch 2023-10-07 19:03:07 +02:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00