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Max Filippov 9e03ade441 target/xtensa: implement MEMCTL SR 
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
..
alpha Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
arm Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
cris Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
i386 x86: implement la57 paging mode 2016-12-22 16:01:04 +01:00
lm32 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
m68k Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
microblaze Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
mips Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
moxie Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
openrisc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
ppc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
s390x Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
sh4 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
sparc Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
tilegx Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
tricore Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
unicore32 Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
xtensa target/xtensa: implement MEMCTL SR 2017-01-15 13:01:56 -08:00