qemu/target
Peter Maydell 5a3c49dedf target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation
The pxa2xx CPUs are now only useful with user-mode emulation, because
we dropped all the machine types that used them in 9.2.  (Technically
you could alse use "-cpu pxa270" with a board model like versatilepb
which doesn't sanity-check the CPU type, but that has never been a
supported config.)

To use them (or iwMMXt emulation) with QEMU user-mode you would need
to explicitly select them with the -cpu option or the QEMU_CPU
environment variable.  A google search finds no examples of anybody
doing this in the last decade; I don't believe the GCC folks are
using QEMU to test their iwMMXt codegen either.  In fact, GCC is in
the process of dropping support for iwMMXT entirely.

The iwMMXt emulation is thousands of lines of code in QEMU, and
is now the only bit of Arm insn decode which doesn't use decodetree.
We have no way to test or validate changes to it. This code is
just dead weight that is almost certainly not being used by anybody.
Mark it as deprecated.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250127112715.2936555-2-peter.maydell@linaro.org
2025-02-07 16:09:17 +00:00
..
alpha accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
arm target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation 2025-02-07 16:09:17 +00:00
avr accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hexagon accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hppa target/hppa: Implement space register hashing for 64-bit HP-UX 2025-01-31 10:05:24 +01:00
i386 * target/i386: optimize string instructions 2025-01-29 09:51:03 -05:00
loongarch target/loongarch: Dump all generic CSR registers 2025-01-24 14:49:24 +08:00
m68k licenses: Remove SPDX tags not being license identifier for Linaro 2025-01-30 13:01:22 +03:00
microblaze accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
mips licenses: Remove SPDX tags not being license identifier for Linaro 2025-01-30 13:01:22 +03:00
openrisc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
ppc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
riscv target/riscv: Support Supm and Sspm as part of Zjpm v1.0 2025-01-19 09:44:35 +10:00
rx fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed 2025-01-28 18:40:19 +00:00
s390x target/s390x: Fix MVC not always invalidating translation blocks 2025-01-30 10:39:37 +01:00
sh4 accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
sparc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
tricore fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed 2025-01-28 18:40:19 +00:00
xtensa target: Replace DEVICE(object_new) -> qdev_new() 2025-01-13 17:06:35 +01:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00