qemu/tcg/riscv
Richard Henderson eafecf0805 tcg: Remove tcg_out_op
All integer opcodes are now converted to TCGOutOp.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-28 13:40:17 -07:00
..
tcg-target-con-set.h tcg/riscv: Drop support for add2/sub2 2025-04-28 13:40:17 -07:00
tcg-target-con-str.h tcg: Convert sub to TCGOutOpSubtract 2025-04-28 13:40:16 -07:00
tcg-target-has.h tcg: Remove INDEX_op_qemu_st8_* 2025-04-28 13:40:17 -07:00
tcg-target-mo.h tcg: Split out tcg-target-mo.h 2025-01-16 20:57:16 -08:00
tcg-target-opc.h.inc tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc 2025-01-16 20:57:16 -08:00
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00
tcg-target.c.inc tcg: Remove tcg_out_op 2025-04-28 13:40:17 -07:00
tcg-target.h tcg: Introduce the 'z' constraint for a hardware zero register 2025-02-18 08:29:03 -08:00