motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-02 23:33:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

tcg: Remove INDEX_op_qemu_st8_*

Browse source 
The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-26 17:34:19 -08:00
parent bf7ca5fb30
commit 33aba058c8
17 changed files with 7 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

6
docs/devel/tcg-ops.rst
View file

@ -744,8 +744,6 @@ QEMU specific operations
qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx*
qemu_st8_i32 *t0*, *t1*, *flags*, *memidx*
- | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest
address *t1*. The _i32/_i64/_i128 size applies to the size of the input/output
register *t0* only. The address *t1* is always sized according to the guest,
@ -763,10 +761,6 @@ QEMU specific operations
64-bit memory access specified in *flags*.
|
| For qemu_ld/st_i128, these are only supported for a 64-bit host.
|
| For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of
the memory operation is known to be 8-bit. This allows the backend to
provide a different set of register constraints.
Host vector operations

4
include/tcg/tcg-opc.h
View file

@ -133,10 +133,6 @@ DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
/* Only used by i386 to cope with stupid register constraints. */
DEF(qemu_st8_i32, 0, 1 + 1, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
/* Only for 64-bit hosts at the moment. */
DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)

1
tcg/aarch64/tcg-target-has.h
View file

@ -14,7 +14,6 @@
/* optional instructions */
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
/*
* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,

1
tcg/arm/tcg-target-has.h
View file

@ -24,7 +24,6 @@ extern bool use_neon_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1

2
tcg/i386/tcg-target-con-str.h
View file

@ -20,7 +20,7 @@ REGS('r', ALL_GENERAL_REGS)
REGS('x', ALL_VECTOR_REGS)
REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st MO_8 data */
/*
* Define constraint letters for constants:

3
tcg/i386/tcg-target-has.h
View file

@ -29,9 +29,6 @@
#if TCG_TARGET_REG_BITS == 64
/* Keep 32-bit values zero-extended in a register. */
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_qemu_st8_i32 0
#else
#define TCG_TARGET_HAS_qemu_st8_i32 1
#endif
#define TCG_TARGET_HAS_qemu_ldst_i128 \

9
tcg/i386/tcg-target.c.inc
View file

@ -2457,7 +2457,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
switch (memop & MO_SIZE) {
case MO_8:
/* This is handled with constraints on INDEX_op_qemu_st8_i32. */
/* This is handled with constraints on INDEX_op_qemu_st_i32. */
tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || datalo < 4);
tcg_out_modrm_sib_offset(s, OPC_MOVB_EvGv + P_REXB_R + h.seg,
datalo, h.base, h.index, 0, h.ofs);
@ -3568,7 +3568,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st8_i32:
tcg_out_qemu_st(s, a0, -1, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
@ -4140,9 +4139,9 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
return C_O1_I1(r, L);
case INDEX_op_qemu_st_i32:
return C_O0_I2(L, L);
case INDEX_op_qemu_st8_i32:
return C_O0_I2(s, L);
return (TCG_TARGET_REG_BITS == 32 && flags == MO_8
? C_O0_I2(s, L)
: C_O0_I2(L, L));
case INDEX_op_qemu_ld_i64:
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) : C_O2_I1(r, r, L);

3
tcg/loongarch64/tcg-target-has.h
View file

@ -9,9 +9,6 @@
#include "host/cpuinfo.h"
/* optional instructions */
#define TCG_TARGET_HAS_qemu_st8_i32 0
/* 64-bit operations */
#define TCG_TARGET_HAS_extr_i64_i32 1

1
tcg/mips/tcg-target-has.h
View file

@ -46,7 +46,6 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0

1
tcg/optimize.c
View file

@ -3192,7 +3192,6 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_qemu_ld_i128:
done = fold_qemu_ld_2reg(&ctx, op);
break;
case INDEX_op_qemu_st8_i32:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st_i128:

2
tcg/ppc/tcg-target-has.h
View file

@ -17,8 +17,6 @@
#define have_vsx (cpuinfo & CPUINFO_VSX)
/* optional instructions */
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0
#endif

1
tcg/riscv/tcg-target-has.h
View file

@ -10,7 +10,6 @@
#include "host/cpuinfo.h"
/* optional instructions */
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 0

1
tcg/s390x/tcg-target-has.h
View file

@ -30,7 +30,6 @@ extern uint64_t s390_facilities[3];
/* optional instructions */
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 1
#define TCG_TARGET_HAS_tst 1

1
tcg/sparc64/tcg-target-has.h
View file

@ -14,7 +14,6 @@ extern bool use_vis3_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_extr_i64_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0
#define TCG_TARGET_HAS_tst 1

9
tcg/tcg-op-ldst.c
View file

@ -270,7 +270,6 @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp *addr,
{
TCGv_i32 swap = NULL;
MemOpIdx orig_oi, oi;
TCGOpcode opc;
tcg_gen_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST);
memop = tcg_canonicalize_memop(memop, 0, 1);
@ -293,12 +292,8 @@ static void tcg_gen_qemu_st_i32_int(TCGv_i32 val, TCGTemp *addr,
oi = make_memop_idx(memop, idx);
}
if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) {
opc = INDEX_op_qemu_st8_i32;
} else {
opc = INDEX_op_qemu_st_i32;
}
gen_ldst(opc, TCG_TYPE_I32, tcgv_i32_temp(val), NULL, addr, oi);
gen_ldst(INDEX_op_qemu_st_i32, TCG_TYPE_I32,
tcgv_i32_temp(val), NULL, addr, oi);
plugin_gen_mem_callbacks_i32(val, NULL, addr, orig_oi, QEMU_PLUGIN_MEM_W);
if (swap) {

4
tcg/tcg.c
View file

@ -2438,9 +2438,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_qemu_st_i64:
return true;
case INDEX_op_qemu_st8_i32:
return TCG_TARGET_HAS_qemu_st8_i32;
case INDEX_op_qemu_ld_i128:
case INDEX_op_qemu_st_i128:
return TCG_TARGET_HAS_qemu_ldst_i128;
@ -3012,7 +3009,6 @@ void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
break;
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st8_i32:
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_ld_i128:

2
tcg/tci/tcg-target-has.h
View file

@ -7,8 +7,6 @@
#ifndef TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_H
#define TCG_TARGET_HAS_qemu_st8_i32 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0
#endif /* TCG_TARGET_REG_BITS == 64 */