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33aba058c8
The i386 backend can now check TCGOP_FLAGS to select the correct set of constraints. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define target-specific opcode support
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* Copyright (c) 2008 Fabrice Bellard
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*/
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#ifndef TCG_TARGET_HAS_H
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#define TCG_TARGET_HAS_H
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#include "host/cpuinfo.h"
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#define have_bmi1 (cpuinfo & CPUINFO_BMI1)
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#define have_popcnt (cpuinfo & CPUINFO_POPCNT)
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#define have_avx1 (cpuinfo & CPUINFO_AVX1)
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#define have_avx2 (cpuinfo & CPUINFO_AVX2)
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#define have_movbe (cpuinfo & CPUINFO_MOVBE)
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/*
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* There are interesting instructions in AVX512, so long as we have AVX512VL,
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* which indicates support for EVEX on sizes smaller than 512 bits.
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*/
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#define have_avx512vl ((cpuinfo & CPUINFO_AVX512VL) && \
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(cpuinfo & CPUINFO_AVX512F))
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#define have_avx512bw ((cpuinfo & CPUINFO_AVX512BW) && have_avx512vl)
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#define have_avx512dq ((cpuinfo & CPUINFO_AVX512DQ) && have_avx512vl)
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#define have_avx512vbmi2 ((cpuinfo & CPUINFO_AVX512VBMI2) && have_avx512vl)
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/* optional instructions */
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#if TCG_TARGET_REG_BITS == 64
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/* Keep 32-bit values zero-extended in a register. */
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#define TCG_TARGET_HAS_extr_i64_i32 1
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#endif
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#define TCG_TARGET_HAS_qemu_ldst_i128 \
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(TCG_TARGET_REG_BITS == 64 && (cpuinfo & CPUINFO_ATOMIC_VMOVDQA))
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#define TCG_TARGET_HAS_tst 1
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/* We do not support older SSE systems, only beginning with AVX1. */
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#define TCG_TARGET_HAS_v64 have_avx1
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#define TCG_TARGET_HAS_v128 have_avx1
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#define TCG_TARGET_HAS_v256 have_avx2
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#define TCG_TARGET_HAS_andc_vec 1
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#define TCG_TARGET_HAS_orc_vec have_avx512vl
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#define TCG_TARGET_HAS_nand_vec have_avx512vl
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#define TCG_TARGET_HAS_nor_vec have_avx512vl
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#define TCG_TARGET_HAS_eqv_vec have_avx512vl
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#define TCG_TARGET_HAS_not_vec have_avx512vl
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#define TCG_TARGET_HAS_neg_vec 0
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_roti_vec have_avx512vl
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#define TCG_TARGET_HAS_rots_vec 0
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#define TCG_TARGET_HAS_rotv_vec have_avx512vl
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec have_avx2
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#define TCG_TARGET_HAS_mul_vec 1
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#define TCG_TARGET_HAS_sat_vec 1
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
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#define TCG_TARGET_HAS_cmpsel_vec 1
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#define TCG_TARGET_HAS_tst_vec have_avx512bw
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#define TCG_TARGET_deposit_valid(type, ofs, len) \
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(((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
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(TCG_TARGET_REG_BITS == 32 && (ofs) == 8 && (len) == 8))
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/*
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* Check for the possibility of low byte/word extraction, high-byte extraction
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* and zero-extending 32-bit right-shift.
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*
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* We cannot sign-extend from high byte to 64-bits without using the
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* REX prefix that explicitly excludes access to the high-byte registers.
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*/
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static inline bool
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tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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switch (ofs) {
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case 0:
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switch (len) {
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case 8:
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case 16:
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return true;
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case 32:
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return type == TCG_TYPE_I64;
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}
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return false;
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case 8:
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return len == 8 && type == TCG_TYPE_I32;
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}
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return false;
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}
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#define TCG_TARGET_sextract_valid tcg_target_sextract_valid
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static inline bool
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tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
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{
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if (type == TCG_TYPE_I64 && ofs + len == 32) {
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return true;
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}
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switch (ofs) {
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case 0:
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return len == 8 || len == 16;
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case 8:
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return len == 8;
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}
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return false;
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}
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#define TCG_TARGET_extract_valid tcg_target_extract_valid
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#endif
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