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f9f99d7ca5
When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:
- define the timers and their access functions
- conditionally add the correct system registers
- create a new accessfn as the rules are subtly different to the
existing secure timer
Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Cc: Andrei Homescu <ahomescu@google.com>
Cc: Arve Hjønnevåg <arve@google.com>
Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
[PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
offset logic now in gt_{indirect,direct}_access_timer_offset() ]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/*
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* Common definitions for Arm Base System Architecture (BSA) platforms.
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*
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* Copyright (c) 2015 Linaro Limited
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#ifndef QEMU_ARM_BSA_H
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#define QEMU_ARM_BSA_H
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/* These are architectural INTID values */
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#define ARCH_TIMER_S_EL2_VIRT_IRQ 19
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#define ARCH_TIMER_S_EL2_IRQ 20
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#define VIRTUAL_PMU_IRQ 23
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#define ARCH_GIC_MAINT_IRQ 25
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#define ARCH_TIMER_NS_EL2_IRQ 26
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#define ARCH_TIMER_VIRT_IRQ 27
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#define ARCH_TIMER_NS_EL2_VIRT_IRQ 28
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#define ARCH_TIMER_S_EL1_IRQ 29
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#define ARCH_TIMER_NS_EL1_IRQ 30
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#define INTID_TO_PPI(irq) ((irq) - 16)
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#endif /* QEMU_ARM_BSA_H */
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