mirror of
https://github.com/Motorhead1991/qemu.git
synced 2025-08-31 22:11:53 -06:00
6262c8addc
According to the AST2700 design, the data source address is 64-bit, with R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0]. Similarly, the digest address is 64-bit, with R_HASH_DIGEST_HI storing bits [63:32] and R_HASH_DIGEST storing bits [31:0]. The HMAC key buffer address is also 64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF storing bits [31:0]. The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, only bits [33:0] are needed to store the DRAM offset. To optimize address storage, the high physical address bits [1:0] of the source, digest and key buffer addresses are stored as dram_offset bits [33:32]. To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensuring that src_addr_hi consists of bits [1:0]. The final src_addr is computed as (src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset within bits [33:0]. Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure that dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as (dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset within bits [33:0]. Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representing the DRAM offset within bits [33:0]. This approach eliminates the need to reduce the high part of the DRAM physical address for DMA operations. Previously, this was calculated as (high physical address bits [7:0] - 4), since the DRAM start address is 0x4_00000000, making the high part address [7:0] - 4. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-14-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
58 lines
1.3 KiB
C
58 lines
1.3 KiB
C
/*
|
|
* ASPEED Hash and Crypto Engine
|
|
*
|
|
* Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates
|
|
* Copyright (C) 2021 IBM Corp.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
|
*/
|
|
|
|
#ifndef ASPEED_HACE_H
|
|
#define ASPEED_HACE_H
|
|
|
|
#include "hw/sysbus.h"
|
|
#include "crypto/hash.h"
|
|
|
|
#define TYPE_ASPEED_HACE "aspeed.hace"
|
|
#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400"
|
|
#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500"
|
|
#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600"
|
|
#define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030"
|
|
#define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700"
|
|
|
|
OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE)
|
|
|
|
#define ASPEED_HACE_MAX_SG 256 /* max number of entries */
|
|
|
|
struct AspeedHACEState {
|
|
SysBusDevice parent;
|
|
|
|
MemoryRegion iomem;
|
|
qemu_irq irq;
|
|
|
|
uint32_t *regs;
|
|
uint32_t total_req_len;
|
|
|
|
MemoryRegion *dram_mr;
|
|
AddressSpace dram_as;
|
|
|
|
QCryptoHash *hash_ctx;
|
|
};
|
|
|
|
|
|
struct AspeedHACEClass {
|
|
SysBusDeviceClass parent_class;
|
|
|
|
const MemoryRegionOps *reg_ops;
|
|
uint32_t src_mask;
|
|
uint32_t dest_mask;
|
|
uint32_t key_mask;
|
|
uint32_t hash_mask;
|
|
uint64_t nr_regs;
|
|
bool raise_crypt_interrupt_workaround;
|
|
uint32_t src_hi_mask;
|
|
uint32_t dest_hi_mask;
|
|
uint32_t key_hi_mask;
|
|
};
|
|
|
|
#endif /* ASPEED_HACE_H */
|