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hw/misc/aspeed_hace: Add support for source, digest, key buffer 64 bit addresses

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According to the AST2700 design, the data source address is 64-bit, with
R_HASH_SRC_HI storing bits [63:32] and R_HASH_SRC storing bits [31:0].
Similarly, the digest address is 64-bit, with R_HASH_DIGEST_HI storing bits
[63:32] and R_HASH_DIGEST storing bits [31:0]. The HMAC key buffer address is also
64-bit, with R_HASH_KEY_BUFF_HI storing bits [63:32] and R_HASH_KEY_BUFF storing
bits [31:0].

The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM addressable range
from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range fits within 34 bits, only
bits [33:0] are needed to store the DRAM offset. To optimize address storage,
the high physical address bits [1:0] of the source, digest and key buffer
addresses are stored as dram_offset bits [33:32].

To achieve this, a src_hi_mask with a mask value of 0x3 is introduced, ensuring
that src_addr_hi consists of bits [1:0]. The final src_addr is computed as
(src_addr_hi[1:0] << 32) | src_addr[31:0], representing the DRAM offset within
bits [33:0].

Similarly, a dest_hi_mask with a mask value of 0x3 is introduced to ensure that
dest_addr_hi consists of bits [1:0]. The final dest_addr is calculated as
(dest_addr_hi[1:0] << 32) | dest_addr[31:0], representing the DRAM offset within
bits [33:0].

Additionally, a key_hi_mask with a mask value of 0x3 is introduced to ensure
that key_buf_addr_hi consists of bits [1:0]. The final key_buf_addr is
determined as (key_buf_addr_hi[1:0] << 32) | key_buf_addr[31:0], representing
the DRAM offset within bits [33:0].

This approach eliminates the need to reduce the high part of the DRAM physical
address for DMA operations. Previously, this was calculated as
(high physical address bits [7:0] - 4), since the DRAM start address is
0x4_00000000, making the high part address [7:0] - 4.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-14-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-05-15 16:09:45 +08:00 • committed by Cédric Le Goater
parent 89d2a9f3f7
commit 6262c8addc
2 changed files with 33 additions and 1 deletions
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31
hw/misc/aspeed_hace.c
View file

@ -30,6 +30,9 @@
#define R_HASH_DIGEST (0x24 / 4)
#define R_HASH_KEY_BUFF (0x28 / 4)
#define R_HASH_SRC_LEN (0x2c / 4)
#define R_HASH_SRC_HI (0x90 / 4)
#define R_HASH_DIGEST_HI (0x94 / 4)
#define R_HASH_KEY_BUFF_HI (0x98 / 4)
#define R_HASH_CMD (0x30 / 4)
/* Hash algorithm selection */
@ -473,6 +476,15 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
}
}
break;
case R_HASH_SRC_HI:
data &= ahc->src_hi_mask;
break;
case R_HASH_DIGEST_HI:
data &= ahc->dest_hi_mask;
break;
case R_HASH_KEY_BUFF_HI:
data &= ahc->key_hi_mask;
break;
default:
break;
}
@ -656,12 +668,29 @@ static void aspeed_ast2700_hace_class_init(ObjectClass *klass, const void *data)
dc->desc = "AST2700 Hash and Crypto Engine";
ahc->nr_regs = 0x64 >> 2;
ahc->nr_regs = 0x9C >> 2;
ahc->src_mask = 0x7FFFFFFF;
ahc->dest_mask = 0x7FFFFFF8;
ahc->key_mask = 0x7FFFFFF8;
ahc->hash_mask = 0x00147FFF;
/*
* The AST2700 supports a maximum DRAM size of 8 GB, with a DRAM
* addressable range from 0x0_0000_0000 to 0x1_FFFF_FFFF. Since this range
* fits within 34 bits, only bits [33:0] are needed to store the DRAM
* offset. To optimize address storage, the high physical address bits
* [1:0] of the source, digest and key buffer addresses are stored as
* dram_offset bits [33:32].
*
* This approach eliminates the need to reduce the high part of the DRAM
* physical address for DMA operations. Previously, this was calculated as
* (high physical address bits [7:0] - 4), since the DRAM start address is
* 0x4_00000000, making the high part address [7:0] - 4.
*/
ahc->src_hi_mask = 0x00000003;
ahc->dest_hi_mask = 0x00000003;
ahc->key_hi_mask = 0x00000003;
/*
* Currently, it does not support the CRYPT command. Instead, it only
* sends an interrupt to notify the firmware that the crypt command

3
include/hw/misc/aspeed_hace.h
View file

@ -50,6 +50,9 @@ struct AspeedHACEClass {
uint32_t hash_mask;
uint64_t nr_regs;
bool raise_crypt_interrupt_workaround;
uint32_t src_hi_mask;
uint32_t dest_hi_mask;
uint32_t key_hi_mask;
};
#endif /* ASPEED_HACE_H */