Tomasz Jeznach 5b128435dc hw/riscv: add riscv-iommu-sys platform device ... This device models the RISC-V IOMMU as a sysbus device. The same design decisions taken in the riscv-iommu-pci device were kept, namely the existence of 4 vectors are available for each interrupt cause. The WSIs are emitted using the input of the s->notify() callback as a index to an IRQ list. The IRQ list starts at 'base_irq' and goes until base_irq + 3. This means that boards must have 4 contiguous IRQ lines available, starting from 'base_irq'. Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241106133407.604587-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-12-20 11:19:16 +10:00
..
boot.h	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
boot_opensbi.h	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	2024-10-30 11:22:07 +10:00
iommu.h	hw/riscv: add riscv-iommu-sys platform device	2024-12-20 11:19:16 +10:00
microchip_pfsoc.h	include: Include headers where needed	2023-01-08 01:54:22 -05:00
numa.h	hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()	2023-01-20 10:14:14 +10:00
opentitan.h	hw/riscv/opentitan: Correct OpenTitanState parent type/size	2023-06-13 17:19:42 +10:00
riscv_hart.h	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	2023-01-06 10:42:55 +10:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.	2023-07-10 22:29:15 +10:00
sifive_u.h	hw/riscv: Move the dtb load bits outside of create_fdt()	2023-03-01 17:19:14 -08:00
spike.h	hw/riscv/spike: use 'fdt' from MachineState	2023-01-20 10:14:13 +10:00
virt.h	hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()	2024-06-26 22:32:29 +10:00