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4f13abcb2b
We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add it. RVG will be used right off the bat in set_misa() of rv64_thead_c906_cpu_init() because the CPU is enabling G via the now removed 'ext_g' flag. After this patch, there are no more MISA extensions represented by flags in RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230406180351.570807-20-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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| arm | ||
| avr | ||
| cris | ||
| hexagon | ||
| hppa | ||
| i386 | ||
| loongarch | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nios2 | ||
| openrisc | ||
| ppc | ||
| riscv | ||
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| sh4 | ||
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| tricore | ||
| xtensa | ||
| Kconfig | ||
| meson.build | ||