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target/rx: Avoid tcg_const_i32
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
09374ee274
commit
daefc08567
1 changed files with 16 additions and 16 deletions
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@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
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static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
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{
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TCGv imm, mem;
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imm = tcg_const_i32(a->imm);
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imm = tcg_constant_i32(a->imm);
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mem = tcg_temp_new();
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tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
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rx_gen_st(a->sz, imm, mem);
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@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
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{
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TCGv z;
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TCGv _imm;
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z = tcg_const_i32(0);
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_imm = tcg_const_i32(imm);
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z = tcg_constant_i32(0);
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_imm = tcg_constant_i32(imm);
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tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
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_imm, cpu_regs[rd]);
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}
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@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
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static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
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{
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TCGv imm = tcg_const_i32(src2);
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TCGv imm = tcg_constant_i32(src2);
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opr(cpu_regs[dst], cpu_regs[src], imm);
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}
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@ -1188,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
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/* emul #imm, rd */
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static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
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{
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TCGv imm = tcg_const_i32(a->imm);
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TCGv imm = tcg_constant_i32(a->imm);
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if (a->rd > 14) {
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qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
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}
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@ -1215,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
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/* emulu #imm, rd */
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static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
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{
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TCGv imm = tcg_const_i32(a->imm);
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TCGv imm = tcg_constant_i32(a->imm);
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if (a->rd > 14) {
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qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
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}
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@ -1585,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
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static inline void rx_save_pc(DisasContext *ctx)
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{
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TCGv pc = tcg_const_i32(ctx->base.pc_next);
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TCGv pc = tcg_constant_i32(ctx->base.pc_next);
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push(pc);
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}
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@ -1668,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
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#define STRING(op) \
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do { \
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TCGv size = tcg_const_i32(a->sz); \
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TCGv size = tcg_constant_i32(a->sz); \
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gen_helper_##op(cpu_env, size); \
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} while (0)
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@ -1799,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
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/* racw #imm */
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static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
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{
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TCGv imm = tcg_const_i32(a->imm + 1);
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TCGv imm = tcg_constant_i32(a->imm + 1);
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gen_helper_racw(cpu_env, imm);
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return true;
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}
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@ -1809,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
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{
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TCGv tmp, z;
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tmp = tcg_temp_new();
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z = tcg_const_i32(0);
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z = tcg_constant_i32(0);
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/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
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tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
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/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
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@ -1831,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
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static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
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cat3(arg_, name, _ir) * a) \
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{ \
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TCGv imm = tcg_const_i32(li(ctx, 0)); \
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TCGv imm = tcg_constant_i32(li(ctx, 0)); \
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gen_helper_##op(cpu_regs[a->rd], cpu_env, \
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cpu_regs[a->rd], imm); \
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return true; \
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@ -1865,7 +1865,7 @@ FOP(FDIV, fdiv)
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/* fcmp #imm, rd */
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static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
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{
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TCGv imm = tcg_const_i32(li(ctx, 0));
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TCGv imm = tcg_constant_i32(li(ctx, 0));
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gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
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return true;
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}
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@ -1962,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
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{ \
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TCGv mask, mem, addr; \
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mem = tcg_temp_new(); \
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mask = tcg_const_i32(1 << a->imm); \
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mask = tcg_constant_i32(1 << a->imm); \
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addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
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cat3(rx_, op, m)(addr, mask); \
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return true; \
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@ -1971,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
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cat3(arg_, name, _ir) * a) \
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{ \
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TCGv mask; \
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mask = tcg_const_i32(1 << a->imm); \
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mask = tcg_constant_i32(1 << a->imm); \
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cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
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return true; \
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} \
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@ -2116,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
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{
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TCGv imm;
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imm = tcg_const_i32(a->imm);
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imm = tcg_constant_i32(a->imm);
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move_to_cr(ctx, imm, a->cr);
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return true;
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}
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@ -2178,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
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TCGv vec;
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tcg_debug_assert(a->imm < 0x100);
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vec = tcg_const_i32(a->imm);
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vec = tcg_constant_i32(a->imm);
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tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
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gen_helper_rxint(cpu_env, vec);
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ctx->base.is_jmp = DISAS_NORETURN;
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