qemu/target/arm/tcg
Peter Maydell f81a5d6863 target/arm: Explicitly select short-format FSR for M-profile
For M-profile, there is no guest-facing A-profile format FSR, but we
still use the env->exception.fsr field to pass fault information from
the point where a fault is raised to the code in
arm_v7m_cpu_do_interrupt() which interprets it and sets the M-profile
specific fault status registers.  So it doesn't matter whether we
fill in env->exception.fsr in the short format or the LPAE format, as
long as both sides agree.  As it happens arm_v7m_cpu_do_interrupt()
assumes short-form.

In compute_fsr_fsc() we weren't explicitly choosing short-form for
M-profile, but instead relied on it falling out in the wash because
arm_s1_regime_using_lpae_format() would be false.  This was broken in
commit 452c67a4 when we added v8R support, because we said "PMSAv8 is
always LPAE format" (as it is for v8R), forgetting that we were
implicitly using this code path on M-profile. At that point we would
hit a g_assert_not_reached():
 ERROR:../../target/arm/internals.h:549:arm_fi_to_lfsc: code should not be reached

#7  0x0000555555e055f7 in arm_fi_to_lfsc (fi=0x7fffecff9a90) at ../../target/arm/internals.h:549
#8  0x0000555555e05a27 in compute_fsr_fsc (env=0x555557356670, fi=0x7fffecff9a90, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff9a1c)
    at ../../target/arm/tlb_helper.c:95
#9  0x0000555555e05b62 in arm_deliver_fault (cpu=0x555557354800, addr=268961344, access_type=MMU_INST_FETCH, mmu_idx=1, fi=0x7fffecff9a90)
    at ../../target/arm/tlb_helper.c:132
#10 0x0000555555e06095 in arm_cpu_tlb_fill (cs=0x555557354800, address=268961344, size=1, access_type=MMU_INST_FETCH, mmu_idx=1, probe=false, retaddr=0)
    at ../../target/arm/tlb_helper.c:260

The specific assertion changed when commit fcc7404eff added
"assert not M-profile" to arm_is_secure_below_el3(), because the
conditions being checked in compute_fsr_fsc() include
arm_el_is_aa64(), which will end up calling arm_is_secure_below_el3()
and asserting before we try to call arm_fi_to_lfsc():

#7  0x0000555555efaf43 in arm_is_secure_below_el3 (env=0x5555574665a0) at ../../target/arm/cpu.h:2396
#8  0x0000555555efb103 in arm_is_el2_enabled (env=0x5555574665a0) at ../../target/arm/cpu.h:2448
#9  0x0000555555efb204 in arm_el_is_aa64 (env=0x5555574665a0, el=1) at ../../target/arm/cpu.h:2509
#10 0x0000555555efbdfd in compute_fsr_fsc (env=0x5555574665a0, fi=0x7fffecff99e0, target_el=1, mmu_idx=1, ret_fsc=0x7fffecff996c)

Avoid the assertion and the incorrect FSR format selection by
explicitly making M-profile use the short-format in this function.

Fixes: 452c67a427 ("target/arm: Enable TTBCR_EAE for ARMv8-R AArch32")a
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1658
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230523131726.866635-1-peter.maydell@linaro.org
(cherry picked from commit d7fe699be5)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-05-31 09:42:37 +03:00
..
a32-uncond.decode
a32.decode
crypto_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
helper-a64.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
hflags.c target/arm: Move hflags code into the tcg directory 2023-02-27 13:27:04 +00:00
iwmmxt_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
m-nocp.decode
m_helper.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
meson.build target/arm: Move hflags code into the tcg directory 2023-02-27 13:27:04 +00:00
mte_helper.c softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accel 2023-03-28 15:24:06 -07:00
mve.decode
mve_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
neon-dp.decode
neon-ls.decode
neon-shared.decode
neon_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
op_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
pauth_helper.c target/arm: Correct AArch64.S2MinTxSZ 32-bit EL1 input size check 2023-05-14 11:25:57 +03:00
psci.c target/arm: Move psci.c into the tcg directory 2023-02-27 13:27:04 +00:00
sme-fa64.decode
sme.decode
sme_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
sve.decode
sve_helper.c target/arm: Fix vd == vm overlap in sve_ldff1_z 2023-05-18 17:56:51 +03:00
t16.decode
t32.decode
tlb_helper.c target/arm: Explicitly select short-format FSR for M-profile 2023-05-31 09:42:37 +03:00
translate-a64.c target/arm: Avoid tcg_const_ptr in handle_rev 2023-03-13 07:03:39 -07:00
translate-a64.h target/arm: Drop new_tmp_a64_zero 2023-03-05 13:44:07 -08:00
translate-m-nocp.c target/arm: Drop tcg_temp_free from translator-m-nocp.c 2023-03-05 13:44:07 -08:00
translate-mve.c target/arm: Avoid tcg_const_* in translate-mve.c 2023-03-13 07:03:39 -07:00
translate-neon.c target/arm: Drop tcg_temp_free from translator-neon.c 2023-03-05 13:44:07 -08:00
translate-sme.c target/arm: Drop tcg_temp_free from translator-sme.c 2023-03-05 13:44:07 -08:00
translate-sve.c target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str} 2023-03-13 07:03:39 -07:00
translate-vfp.c target/arm: Create gen_set_rmode, gen_restore_rmode 2023-03-13 06:44:38 -07:00
translate.c target/arm: Define and use new load_cpu_field_low32() 2023-05-10 20:50:38 +03:00
translate.h target/arm: Create gen_set_rmode, gen_restore_rmode 2023-03-13 06:44:38 -07:00
vec_helper.c target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
vec_internal.h target/arm: move helpers to tcg/ 2023-02-27 13:27:04 +00:00
vfp-uncond.decode
vfp.decode