Richard Henderson 169d253e1f tcg/riscv: Fix typo in tgen_extract ... Fix the direction of the shift, introduced when converting the codebase to TCGOutOp* and small tgen_* helpers. Fixes: 5a4d034f3c ("tcg: Convert extract to TCGOutOpExtract") Reported-by: Andrea Bolognani <abologna@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Andrea Bolognani <abologna@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2025-06-30 07:42:38 -06:00
..
tcg-target-con-set.h	tcg/riscv: Drop support for add2/sub2	2025-04-28 13:40:17 -07:00
tcg-target-con-str.h	tcg: Convert sub to TCGOutOpSubtract	2025-04-28 13:40:16 -07:00
tcg-target-has.h	tcg: Remove INDEX_op_qemu_st8_*	2025-04-28 13:40:17 -07:00
tcg-target-mo.h	tcg: Split out tcg-target-mo.h	2025-01-16 20:57:16 -08:00
tcg-target-opc.h.inc	tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc	2025-01-16 20:57:16 -08:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/riscv: Fix typo in tgen_extract	2025-06-30 07:42:38 -06:00
tcg-target.h	tcg: Introduce the 'z' constraint for a hardware zero register	2025-02-18 08:29:03 -08:00