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Bibo Mao d41989e754 target/loongarch: Use actual operand size with vbsrl check 
Hardcoded 32 bytes is used for vbsrl emulation check, there is
problem when options lsx=on,lasx=off is used for vbsrl.v instruction
in TCG mode. It injects LASX exception rather LSX exception.

Here actual operand size is used.

Cc: qemu-stable@nongnu.org
Fixes: df97f33807 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve")
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-27 11:32:33 +08:00
..
alpha accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
arm accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
avr accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hexagon accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hppa accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
i386 accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
loongarch target/loongarch: Use actual operand size with vbsrl check 2024-12-27 11:32:33 +08:00
m68k accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
microblaze accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
mips accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
openrisc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
ppc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
riscv accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
rx accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
s390x accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
sh4 accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
sparc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
tricore accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
xtensa accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00