qemu/target
Peter Maydell 2b3bfbb21b target/i386: Do not raise Invalid for 0 * Inf + QNaN
In commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in
pick_nan_muladd") we changed the handling of 0 * Inf + QNaN to always
raise the Invalid exception regardless of target architecture.  (This
was a change affecting hppa, i386, sh4 and tricore.) However, this
was incorrect for i386, which documents in the SDM section 14.5.2
that for the 0 * Inf + NaN case that it will only raise the Invalid
exception when the input is an SNaN.  (This is permitted by the IEEE
754-2008 specification, which documents that whether we raise Invalid
for 0 * Inf + QNaN is implementation defined.)

Adjust the softfloat pick_nan_muladd code to allow the target to
suppress the raising of Invalid for the inf * zero + NaN case (as an
extra flag orthogonal to its choice for when to use the default NaN),
and enable that for x86.

We do not revert here the behaviour change for hppa, sh4 or tricore:
 * The sh4 manual is clear that it should signal Invalid
 * The tricore manual is a bit vague but doesn't say it shouldn't
 * The hppa manual doesn't talk about fused multiply-add corner
   cases at all

Cc: qemu-stable@nongnu.org
Fixes: 8adcff4ae7 (""fpu: handle raising Invalid for infzero in pick_nan_muladd")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20250116112536.4117889-2-peter.maydell@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-07 15:51:01 +01:00
..
alpha accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
arm target/arm: Use FPST_A64_F16 for halfprec-to-other conversions 2025-01-28 18:40:19 +00:00
avr accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hexagon accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
hppa target/hppa: Implement space register hashing for 64-bit HP-UX 2025-01-31 10:05:24 +01:00
i386 target/i386: Do not raise Invalid for 0 * Inf + QNaN 2025-02-07 15:51:01 +01:00
loongarch target/loongarch: Dump all generic CSR registers 2025-01-24 14:49:24 +08:00
m68k licenses: Remove SPDX tags not being license identifier for Linaro 2025-01-30 13:01:22 +03:00
microblaze accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
mips licenses: Remove SPDX tags not being license identifier for Linaro 2025-01-30 13:01:22 +03:00
openrisc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
ppc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
riscv target/riscv: Support Supm and Sspm as part of Zjpm v1.0 2025-01-19 09:44:35 +10:00
rx fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed 2025-01-28 18:40:19 +00:00
s390x target/s390x: Fix MVC not always invalidating translation blocks 2025-01-30 10:39:37 +01:00
sh4 accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
sparc accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core 2024-12-24 08:32:15 -08:00
tricore fpu: Rename float_flag_output_denormal to float_flag_output_denormal_flushed 2025-01-28 18:40:19 +00:00
xtensa target: Replace DEVICE(object_new) -> qdev_new() 2025-01-13 17:06:35 +01:00
Kconfig target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00
meson.build target/cris: Remove the deprecated CRIS target 2024-09-13 20:11:13 +02:00